PPT-Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks

George Michelogiannakis Nan Jiang Daniel Becker William J Dally Stanford University MICRO 44 37 December 2011 Porto Allegre Brazil Introduction Performance sensitive to allocator performance. Veronica . Eyo. Sharvari. Joshi. On-chip interconnect network/ . NoC. The layered-stack approach to the design of the on-chip . intercore. communications is called the Network-on-Chip (NOC) methodology. Natalie . Enright. . Jerger. Introduction. How to connect individual devices into a group of communicating devices?. A device can be:. Component within a chip. Component within a computer. Computer. Router . Microarchitecture. & Network Topologies. Daniel U. Becker,. James Chen, Nan Jiang,. Prof. William J. Dally. Concurrent VLSI Architecture Group. Stanford University. Outline. Introduction. George . Michelogiannakis. , Nan Jiang,. Daniel Becker, William J. Dally. Stanford University. MICRO 44, 3-7 December 2011, Porto . Allegre. , Brazil. Introduction. Performance sensitive to allocator performance. IeTF78 (Maastricht) – July 25-30 2010. Sriganesh Kini. David sinicrope. Problem statement. Need for a packet service that can carry . any. protocol (similar to an Ethernet pseudowire). Service should be efficient for the most common protocol carried by the service. 6. Bodie, Kane, and Marcus. Essentials of Investments, . 9. th. Edition. 6.1 Diversification and Portfolio Risk. Market/Systematic/Nondiversifiable Risk. Risk factors common to whole economy. Unique/Firm-Specific/Nonsystematic/ Diversifiable Risk. Adil Kidwai. Intel Corporation, Hillsboro. Outline. Motivation – product targets. Architecture . overview – Single-chip . WiFi. Issues and Mitigation Techniques. Multi-standard coexistence in Single-chip. Daniel U. Becker. PhD Oral Examination. 8/21/2012. Concurrent. VLSI. Architecture. Group. Outline. INTRODUCTION. Allocator Implementations. Buffer Management. Infrastructure. Conclusions. Efficient Microarchitecture for NoC Routers. Network Performance Measurement. Srinivas Narayana. MIT CSAIL. An example: High tail latencies. Delay completion of flows. (and applications). An example: High tail latencies. Where is the queue buildup?. Reetuparna. Das. €. §. . Onur. Mutlu. †. . Thomas Moscibroda. ‡. . Chita Das. §. € . Intel Labs . §. PennState. . †. CMU . ‡. Microsoft Research. Network-on-Chip. Network-on-Chip. Reetuparna. Das. €. §. . Onur. Mutlu. †. . Thomas Moscibroda. ‡. . Chita Das. §. € . Intel Labs . §. PennState. . †. CMU . ‡. Microsoft Research. Network-on-Chip. Network-on-Chip. Reetuparna. Das. €. §. . Onur. Mutlu. †. . Thomas Moscibroda. ‡. . Chita Das. §. € . Intel Labs . §. PennState. . †. CMU . ‡. Microsoft Research. Network-on-Chip. Network-on-Chip. Fall 2019. Programmable Scheduling. Scheduling in switch pipelines. Packets wait in buffers/queues until serviced. Two possibilities: . Input-queued. vs. . output-queued. Suppose there are pkts on port 1 to both 2 and 3. Reetuparna Das. §. . Onur Mutlu. †. Thomas Moscibroda. ‡. Chita Das. §. §. Pennsylvania State University . †. Carnegie Mellon University . ‡. Microsoft Research. The Problem: Packet Scheduling.