PDF-SNA SNLS SNA SNLS BIT SHIFT REGISTERS SDLS MARCH REVISED MARCH POST OFFICE BOX DALLAS

Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters brPage 2br SN5491A SN54LS91 SN7491A SN74LS91 8BIT SHIFT REGISTERS SDLS126 MARCH 197. 270Inch Character Height TIL308 Has Left Decimal TIL309 Has Right Decimal Easy System Interface Wide Viewing Angle Internal TTL MSI Chip With Latch Decoder and Driver ConstantCurrent Drive for LightEmitting Diodes mechanical data These assemblies con Products conform to specifications per the terms of Te xas Instruments standard warranty Production processing does not necessarily include testing of all parameters BW 87223 dB 70 MHz Matched 05dB Attenuators for Contrast Control Three Externall Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters brPage 2br SN54LS181 SN54S181 SN74LS181 SN74S181 ARITHMETIC LOGIC UNITSFUNCTION GENE In highperformance memory systems these devices can minimize the effects of system decoding When employed with highspeed memories utilizing a fastenable circuit the delay times of these decoders and the enable time of the memory are usually less tha Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters brPage 2br SN54LS292 SN54LS294 SN74LS292 SN74LS294 PROGRAMMABLE FREQUENCY DIVIDERSDI Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters brPage 2br SN54LS673 SN54LS674 SN74LS673 SN74LS674 16BIT SHIFT REGISTERS SDLS195 MA Two functionselect S0 S1 inputs and two output enable OE1 OE2 inputs can be used to choose the modes of operation listed in the function table Synchronous parallel loading is accomplished by taking both S0 and S1 high This places the 3state output 15 CP 0 15 CG 0 15 CO 1 2 4 8 This symbol is in accordance with ANSIIEEE Std 911984 and IEC Publication 61712 4 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A B GND GND GND GND CC CC S0 S1 S2 S3 DW PACKAGE TOP VIEW EPIC is a trademark Products conform to specifications per the terms of Te xas Instruments standard warranty Production processing does not necessarily include testing of all parameters BW 87223 dB 70 MHz Matched 05dB Attenuators for Contrast Control Three Externall Organizatio n 16K Single 5V Power Supply Pin Compatible With Existing 128K MOS ROMs PROMs and EPROMs All InputsOutputs Fully TTL Compatible Max AccessMin Cycle Times CC 10 27C12812 120 ns 27CPC12815 150 ns 27CPC12820 200 ns 27CPC12825 250 ns Power S Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters brPage 2br SN54LS445 SN74LS445 BCDTODECIMAL DECODERSDRIVERS SDLS177 NOVEMBER 1977 Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters brPage 2br SN5476 SN54LS76A SN7476 SN74LS76A DUAL JK FLIPFLOPS WITH PRESET AND CLEAR Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters brPage 2br SN54190 SN54191 SN54LS190 SN54LS191 SN74190 SN74191 SN74LS190 SN74LS191 S Parallelin access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shiftload SHLD input These registers also feature gated clock CLK inputs and complementary outputs from the eighth bit A