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Circuits from RF to Bits Circuits from RF to Bits

Circuits from RF to Bits - PowerPoint Presentation

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Circuits from RF to Bits - PPT Presentation

EE194 Brad Wheeler Block Diagram RF gain N oise reasons Downconversion Easier to build low frequency circuits Signal processing M ore gain filtering Digitizationdemodulation Extract the information ID: 673460

filter passive circuits gain passive filter gain circuits time ieee noise behzad razavi state capacitor design active power filters

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Slide1

Circuits from RF to BitsEE194

Brad WheelerSlide2

Block Diagram

RF gain

N

oise reasonsDown-conversionEasier to build low frequency circuitsSignal processing More gain, filteringDigitization/demodulationExtract the informationSlide3

To LNA or Not to LNA?

Low Noise Amplifier (LNA) provides RF gain

LNA Design Recipe

Start with common source/gateAdd inductorsBurn lots of currentProsLower Noise Figure

Better sensitivity

Cons

Power consumption

Razavi

,

Behzad

, and

Razavi

Behzad

RF microelectronics

. Vol. 2. New Jersey: Prentice Hall, 1998.Slide4

Matching Networks

Achieve RF gain using LC resonance instead of active elements

Topologies

L, Pi, tapped elementMetricsGainMust account for loadingInput impedanceBandwidthTuningNoise

Cr: Prof

Niknejad

, EE142Slide5

Matching Network Gain

Series to parallel transformation

Loaded vs unloaded

Realistic on-chip inductors

Q

~

10-15+

L ~ pH to

nH

(10nH roughly 200um*200um)

 Slide6

Matching Network Gain

UnloadedSlide7

Matching Network Gain

Unloaded

Loaded, Q=15Slide8

Down-Conversion Mixers

Move signal from RF (GHz) to Intermediate Frequency (MHz)

Metrics

Input impedanceGainNoiseLinearityPassive vs Active

Razavi

,

Behzad

, and

Razavi

Behzad

RF microelectronics

. Vol. 2. New Jersey: Prentice Hall, 1998.Slide9

Passive Mixers

Input impedance

Noise

Gain

Sinc

(Duty Cycle)

Razavi

,

Behzad

, and

Razavi

Behzad

RF microelectronics

. Vol. 2. New Jersey: Prentice Hall, 1998.Slide10

Passive Mixers

Transparency

N-path filter

Limited by Ron/RsAndrews/MolnarHard switching, multiple phasesCook/BernyResonant, sinusoidal driveSlide11

Hard Switching

Rail to rail switch drivers

Multiple clock phases, non-overlapping inputs

Higher performance, higher power to drive

Andrews, Caroline, and

Alyosha

C. Molnar. "Implications of passive mixer transparency for impedance matching and noise figure in passive mixer-first receivers." 

IEEE Transactions on Circuits and Systems I: Regular Papers

 57.12 (2010): 3092-3103.Slide12

Sinusoidal Drive

Can also resonate out switch gate capacitance in LC tank

Sinusoidal waveform yields approximately square conduction cycle

Lower LO power, but fewer phases available

Cook, Ben W., et al. "Low-power 2.4-GHz transceiver with passive RX front-end and 400-mV supply." 

IEEE Journal of Solid-State Circuits

 41.12 (2006): 2757-2766.Slide13

Receiver Components

RF gain

Noise reasons

Down-conversionEasier to build low frequency circuitsSignal processing More gain, filteringDigitization/demodulationExtract the informationSlide14

IF Amplifiers

Direct conversion vs heterodyne

DC offsets, flicker noise

We need amplifiers/filters in the MHz rangeFirst active amplifier becomes the noise vs power limiting factorSlide15

Filters

Why filter?

Interference

NoiseMore options than Baskin RobbinsDiscrete time (DT) vs continuous time (CT)AliasingActive vs passiveSlide16

CT Filters

Cr: Prof

Boser

, EE240C

Tow-Thomas

Biquad

Active Ladder Filter

Gm-C Filter

Passive Ladder FilterSlide17

Filter Frequency Ranges

Cr: Prof

Boser

, EE240CSlide18

(Active) Switched Capacitor

Transfer function set by clocks, capacitor ratios

Very precise control

Active = Charge being pushed around by

opamps

Cr: Prof

Boser

, EE240CSlide19

Passive Switched Capacitor

Transconductor

converts input to charge

Passive charge sharing defines filteringPoles determined by capacitor ratios

Tohidian

,

Massoud

, Iman

Madadi

, and Robert

Bogdan

Staszewski

. "Analysis and design of a high-order discrete-time passive IIR low-pass filter." 

IEEE Journal of Solid-State Circuits

 49.11 (2014): 2575-2587.

 

Continuous time gain and anti-alias filtering

Discrete time filtering

 

 Slide20

High Order Poles

One

transconductor

, many switches and capsCan only implement poles on the real axis with this topology

Tohidian

,

Massoud

, Iman

Madadi

, and Robert

Bogdan

Staszewski

. "Analysis and design of a high-order discrete-time passive IIR low-pass filter." 

IEEE Journal of Solid-State Circuits

 49.11 (2014): 2575-2587.Slide21

Complex Conjugate Poles

Negative feedback allows to move poles off real axis

Limited to low quality factor

Invert Polarity

Lulec

,

Sevil

Zeynep

, David A. Johns, and Antonio

Liscidini

. "A simplified model for passive-switched-capacitor filters with complex poles." 

IEEE Transactions on Circuits and Systems II: Express Briefs

 63.6 (2016): 513-517.Slide22

Complex Filters

By combining charge from In-phase and Quadrature samples, can make filters asymmetric about 0 Hz

Madadi

, Iman,

Massoud

Tohidian

, and Robert Bogdan

Staszewski

. "Analysis and design of I/Q charge-sharing band-pass-filter for

superheterodyne

receivers." 

IEEE Transactions on Circuits and Systems I: Regular Papers

 62.8 (2015): 2114-2121.Slide23

Passive FIR

Cook, Benjamin W., and Axel D. Berny. "Passive discrete time analog filter." U.S. Patent No. 8,849,886. 30 Sep. 2014.

 

 Slide24

Previous Filter Design

Cascade of IIR & FIR blocks

4

th order filter centered at 2.5MHz with Fs = 100 MHz1-bit zero crossing demodulatorHigh sampling frequencyGain requirementsOffset cancellation

(Simulated)Slide25

ADC/Comparator

Sample rate, number of bits,

etc

driven by system level modelingFilter type/passbandDemodulatorSimplest ADC is just a comparator (1-bit)Demodulate FSK by counting time between zero crossings of square waveSlide26

Clocked Comparators

Razavi

,

Behzad

. "The

StrongARM

Latch [A Circuit for All Seasons]." 

Solid-State Circuits Magazine, IEEE

 7.2 (2015): 12-17.

Schinkel, Daniel, et al. "A double-tail latch-type voltage sense amplifier with 18ps setup+ hold time." 

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

. IEEE, 2007.

Strongarm

Double TailSlide27

Design Considerations

Power, offset, speed, noise

Lower offset either by up-sizing input devices, or by adding correction

Both cost more powerPelgrom, Monte CarloOffset calibration schemesCurrent tuningCapacitor DACBody biasSlide28

Simulation Issues

Switched capacitor circuits require special simulation techniques

Periodic Steady State (PSS)

Compute a solution around a time varying operating pointPeriodic Versions of all the normal analysisPACPNoise