Datao Gong Jingbo Ye Southern Methodist University US Outline Cable model comparison GBCR block diagram update CDR simulation Summary 2 Cable models comparision We have compared two models under the same stimuluses and loads ID: 1030647
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1. GBCR StatusChufeng Chen, Quan Sun, Datao Gong, Jingbo Ye Southern Methodist University (US)
2. OutlineCable model comparisonGBCR block diagram updateCDR simulationSummary2
3. Cable models comparisionWe have compared two models under the same stimuluses and loads.Model used by SMU team is close to the measurement results. But some issues still exist.We discussed with Seigen Uni team about the model. They will update their simulator to work on mixed-mode touchstone file as SMU team do.However, simulation of the cable model in the cadence may not accurate enough. And the performance of an equalizer will be sensitive to PVT and radiation.We will make our effort on getting a clean eye diagram by using the equalizer + the CDR.Low-frequency attenuation is large in the SMU’s model.Why?3
4. GBCR Block Diagram4VCMProgrammable equalization1.2 Vpp,PRBS1550 Ω50 Ω50 Ω50 ΩEqualizerLimiterCDRCML DriverGBCRThe CDR obtained from lpGBT project do not need standalone decision circuits. It internally includes decision circuits in the phase detector.It include circuits to bypass decision. No bypassing circuits need to be implemented.The CDR will be changed for 5.12 Gb/sWe propose a 2mm X 3mm area for the first prototype.Bypass CDRBlocks that have been studied preliminarily.Blocks that have been obtained from lpBGT project(silicon proved)Blocks that will be downgraded from previous design
5. CDR simulationBehavioral simulation of the analog core of the CDR in lpGBT is carried out.The loop locked as expected.We will run transistor level simulation in next step.5
6. SummaryStudied and compared cable models. The attenuation at the low frequency is not reasonable.The jitter of the diagram is sensitive to the equalizer’s parameter, especially in a radiation environment.Updated block diagram.CDR works at behavior level in our simulation.We are having some transistor level issues in the simulation and is on close contact with one of the CDR designers to work this out before we can move forward in changing the circuit for 5.12 Gb/s.6