Timer count ex TA0R Interrupt Note Timer Settings Upmode CCR07 CCR1 7 CCR21 Interrupts Enabled CCR1CCR2overflow CCR1 Interrupt overflow Interrupt CCR2 Interrupt ID: 626548
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Slide1
6
7
0
1
5
ACLK
(32.768kHz)
Timer count
(ex. TA0R)
Interrupt
Note:
Timer Settings :
Upmode
/ CCR0=7 / CCR1 =7/ CCR2=1
Interrupts
Enabled: CCR1/CCR2/overflow
CCR1
Interrupt
overflow
Interrupt
CCR2
Interrupt
B
A
C
Normal operationSlide2
Case A: Pattern1
Timer is cleared in A duration command : TA0CTL |= (MC_1 | TACLR);
6
7
0
1
5
ACLK
(32.768kHz)
Timer count
(ex. TA0R)
Interrupt
CCR1
Interrupt
overflow
Interrupt
CCR2
Interrupt
Timer
Clear
0Slide3
Case A: Pattern 2Timer is cleared in A duration
command : TA0CTL |= (MC_1 | TACLR);
6
7
0
5
ACLK
(32.768kHz)
Timer count
(ex. TA0R)
Interrupt
CCR1
Interrupt
overflow
Interrupt
CCR2
Interrupt
Timer
Clear
0Slide4
Case B: Pattern 1Timer is cleared in B duration
command : TA0CTL |= (MC_1 | TACLR);
6
7
0
2
5
ACLK
(32.768kHz)
Timer count
(ex. TA0R)
Interrupt
CCR1
Interrupt
CCR2
Interrupt
Timer
Clear
1Slide5
Case B: Pattern2Timer is cleared in B duration
command : TA0CTL |= (MC_1 | TACLR);
6
7
0
1
5
ACLK
(32.768kHz)
Timer count
(ex. TA0R)
Interrupt
CCR1
Interrupt
CCR2
Interrupt
Timer
Clear
0Slide6
Case B: Pattern3Timer is cleared in B duration
command : TA0CTL |= (MC_1 | TACLR);
6
7
0
1
5
ACLK
(32.768kHz)
Timer count
(ex. TA0R)
Interrupt
CCR1
Interrupt
CCR2
Interrupt
Timer
ClearSlide7
Case B: Pattern4Timer is cleared in B duration
command : TA0CTL |= (MC_1 | TACLR);
6
7
1
2
5
ACLK
(32.768kHz)
Timer count
(ex. TA0R)
Interrupt
CCR1
Interrupt
CCR2
Interrupt
Timer
ClearSlide8
Case C: Pattern 1Timer is cleared in C duration
command : TA0CTL |= (MC_1 | TACLR);
6
7
1
2
5
ACLK
(32.768kHz)
Timer count
(ex. TA0R)
Interrupt
CCR1
Interrupt
CCR2
Interrupt
Timer
Clear
0Slide9
Case C: Pattern 2Timer is cleared in C duration
command : TA0CTL |= (MC_1 | TACLR);
6
7
0
1
5
ACLK
(32.768kHz)
Timer count
(ex. TA0R)
Interrupt
CCR1
Interrupt
CCR2
Interrupt
Timer
Clear
0Slide10
Case C: Pattern3Timer is cleared in C duration
command : TA0CTL |= (MC_1 | TACLR);
6
7
0
2
5
ACLK
(32.768kHz)
Timer count
(ex. TA0R)
Interrupt
CCR1
Interrupt
CCR2
Interrupt
Timer
Clear
1Slide11
Case C: Pattern4Timer is cleared in C duration
command : TA0CTL |= (MC_1 | TACLR);
6
7
0
1
5
ACLK
(32.768kHz)
Timer count
(ex. TA0R)
Interrupt
CCR1
Interrupt
CCR2
Interrupt
Timer
Clear
0Slide12
Case C: Pattern5Timer is cleared in C duration
command : TA0CTL |= (MC_1 | TACLR);
6
7
1
2
5
ACLK
(32.768kHz)
Timer count
(ex. TA0R)
Interrupt
CCR1
Interrupt
CCR2
Interrupt
Timer
ClearSlide13
Case C: Pattern6Timer is cleared in C duration
command : TA0CTL |= (MC_1 | TACLR);
6
7
0
1
5
ACLK
(32.768kHz)
Timer count
(ex. TA0R)
Interrupt
CCR1
Interrupt
CCR2
Interrupt
Timer
Clear