P Du W Zhao SH Weng CK Cheng and R Graham UC San Diego ckchengucsdedu 1 Outline Introduction Problem Formulation Character Design for Wire Layouts Character Design and Stencil Compaction for Via Layouts ID: 618400
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Character Design and Stamp Algorithms for Character Projection Electron-Beam Lithography
P. Du, W. Zhao, S.H. Weng,C.K. Cheng, and R. GrahamUC San Diegockcheng@ucsd.edu
1Slide2
OutlineIntroduction
Problem FormulationCharacter Design for Wire LayoutsCharacter Design and Stencil Compaction for Via LayoutsExperimental ResultsConclusion2Slide3
Introduction
Electron Beam Lithography (EBL): maskless fabricationVariable Shaped Beam (VSB): variant rectangles for the layoutCharacter Projection (CP): improves VSB throughput
3
Wire Layout
Via LayoutSlide4
Previous Works of CP
Previous Character DesignsRows of wire segments with various separationArrays of viasUsageApply Characters to stamp most wires and viasUse VSB to patch up the rest wires and
vias
4Slide5
Problem Formulation
Character and Stencil designs:Prescribe a set of characters and assemble in a stencil.Stamp algorithm:Match the characters to the most of layout
One stencil for wires and the other for
vias
5Slide6
Wire Layout
Layout is cut into blocks of size cx
x
c
y
.
Wire layout on grid with
unit size
u
x
and u
y
.
6Slide7
Stamp Process
7Assumption of character projectionArbitrary shifting
Arbitrary rectangular masking
Projected regions can overlapSlide8
Normalization of Wire Layouts
Segment: a column of wire grid in the blockNormalization: expand the wires in each segment into four types.
8Slide9
Segments Categorization
Type 1: A segment split into two wiresType 2: A wire with a gap on the top.Type 3: A wire with no gaps. Type 4: A segment split into 3 or more wires.9Slide10
Character Design for Wire Layouts
A character starts with Type 1 segment followed by cx-1 segments of Type 2 and 3.The number of Type 2 segments is no more than a constant
B
g
.
10Slide11
Stamp Algorithm for Wire Layouts
11Cut layout into rows of height c
y
.
Cut each
row
into
groups at Types 1 and 4 segments.
Match the characters greedily from left to right.Slide12
Experimental Results
12Slide13
Experimental Results
The row heights are chosen dynamically to balance the overhead of dummy fill against the improvement of CP.13Slide14
Experimental Results
14Improvement vs. overhead of dummy fill.Slide15
Via Layout
Assumption: Vias are of the same size and on the grids.Observation: Vias are sparse comparing to wires.15Slide16
Character Design for Via Layouts
Characters: k vias linked in a path of length w.The paths are oriented in top-right direction.Three characters are shown in the figures (k=3)16Slide17
Stencils: Character Compaction
17A single via v
at center and
two
vias
at I and III quadrants.
Vias
at quadrants are aligned for
each length
w.Example: Three windows in the figure correspond to three characters.Slide18
Stamp Algorithm for Via Layouts
Construct a directed acyclic graph G(V,E).The vertex set V contains all vias.An edge
(
u,v
)
belongs to
E
if and only if
v
is in the first quadrant of
u
with distance less than w.
Use
the minimum vertex-disjoint path cover algorithm to match characters with the layout.
18Slide19
Experimental Results
Improvement: average number of vias per shotPath length: upper bound of ImprovementImprovement increases with Character Size and Path Length.
19Slide20
Conclusion
A framework includes character design, stencil compaction and layout matching algorithms.For wires, we normalize the wires with dummy fills and expansion.For vias, we devise k-via sets and compact the sets into a stencil. A path covering algorithm maps the set.The approach improves the throughput of manufacturing over VSB.
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Thank you for your attention!
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