Presentation on theme: "HCC Derived Clocks"— Presentation transcript
Slide1
HCC Derived ClocksSlide2
Generated Clocks
The HCC generates two clocks from the
ePLL
160 MHz clocks and the chip 40 MHz clock, used as a reference:An 80 MHz clock using a divide by 2 circuit that contains no loops and so is self clearing.A 40 MHz clock that should be less sensitive to perturbations in the GBT supplied clock.
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HCC Derived Clocks
2Slide3
div2 Circuit
Positive and Negative edges of 40 MHz clock produce pulses into second DFF. These are sampled at 160
MHz.
Simulations show circuit working for most phases between 40 and 160 MHz clocks (~200
ps
out of 6.25ns fail) and for 50/50, 25/75, 75/25 duty cycle on 40
MHz.
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HCC Derived Clocks
3Slide4
div4 Circuit
Circuit samples reference 40 MHz clock at 160 MHz into a 4-bit shift register.
40 MHz clock is generated by separate 4-bit shift register at 160 MHz
clk[3:0] <= {clk[2:0], ~clk[1]};
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HCC Derived Clocks
4Slide5
div4 Local Reset
Set by external reset
Set by 4 mismatches between reference and generated 40 MHz sampled shift registers
Loads reference 40 MHz shift register into generated 40 MHz shift registerCount of local resets made available in a register40 April 2014
HCC Derived Clocks
5Slide6
div4 simulation
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HCC Derived Clocks
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3.25 ns phase
3.25 ns phase
Error count
Local Reset Pulse
Extra pulseSlide7
div4 Simulation (2)
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HCC Derived Clocks
7
Long PulseSlide8
div4 To Do
U
nderstand reasonable failure modes on 40 MHz from GBT
Simulate with ePll response includedExplore phasing between ref 40 MHz and 160 MHzAre there failure modes of this approach?
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HCC Derived Clocks
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