Probabilistic modelling of performance parameters of Carbon Nanotube - PowerPoint Presentation

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Probabilistic modelling of performance parameters of Carbon Nanotube transistors

Department of Electrical and Computer Engineering

By

Yaman Sangar

Amitesh Narayan

Snehal Mhatre

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Overview

MotivationIntroductionCMOS v/s CNTFETsCNT Technology - ChallengesProbabilistic model of faultsModelling performance parameters:ION / IOFF tuning ratioGate delayNoise MarginConclusion

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Overview

MotivationIntroductionCMOS v/s CNTFETsCNT Technology – ChallengesProbabilistic model of faultsModelling performance parameters:ION / IOFF tuning ratioGate delayNoise MarginConclusion

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MOTIVATION: Why CNTFET?

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Dennard Scaling might not last long

Increased performance by better algorithms?

More parallelism?

Alternatives to CMOS -

FinFETs

,

Ge

-nanowire FET, Si-nanowire FET, wrap-around gate

MOS,

graphene

ribbon FET

What about an inherently faster and less power consuming device?

Yay CNTFET – faster with low power

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Overview

MotivationIntroductionCMOS v/s CNTFETsCNT Technology – ChallengesProbabilistic model of faultsModelling performance parameters:ION / IOFF tuning ratioGate delayNoise MarginConclusion

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Carbon Nanotubes

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Types of CNTs

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Single Walled CNT (SWNT)Double Walled CNT (DWNT)Multiple Walled CNT (MWNT)Depending on Chiral angle:Semiconducting CNT (s-CNT)Metallic CNT (m-CNT)

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Properties of CNTs

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Strong and very flexible molecular material

Electrical conductivity is 6 times that of copper

High current carrying capacity

Thermal conductivity is 15 times more than copper

Toxicity?

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CNTFET

How CNTs conduct?

Gate used to electrostatically induce carriers into tubeBallistic Transport

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Overview

MotivationIntroductionCMOS v/s CNTFETsCNT Technology – ChallengesProbabilistic model of faultsModelling performance parameters:ION / IOFF tuning ratioGate delayNoise MarginConclusion

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CircuitFETDelay (In Picoseconds)Power (In uWatts)InverterCMOS16.589.81CNT3.780.252 Input NandCMOS24.3220.67CNT5.980.692 Input NorCMOS39.2622.13CNT6.490.48

Simulation based Comparison

between CMOS and CNT technology

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Better delay

Circuit

FETDelay (In Picoseconds)Power (In uWatts)InverterCMOS16.589.81CNT3.780.252 Input NandCMOS24.3220.67CNT5.980.692 Input NorCMOS39.2622.13CNT6.490.48

Simulation based Comparison

between CMOS and CNT technology

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Better delay

At lower power!

CircuitFETDelay (In Picoseconds)Power (In uWatts)InverterCMOS16.589.81CNT3.780.252 Input NandCMOS24.3220.67CNT5.980.692 Input NorCMOS39.2622.13CNT6.490.48

Simulation based Comparison

between CMOS and CNT technology

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Overview

MotivationIntroductionCMOS v/s CNTFETsCNT Technology – ChallengesProbabilistic model of faultsModelling performance parameters:ION / IOFF tuning ratioGate delayNoise MarginConclusion

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Major CNT specific variationsCNT density variationMetallic CNT induced count variationCNT diameter variationCNT misalignmentCNT doping variation

Challenges with CNT technology

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Unavoidable process variations

Performance parameters affected

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CNT density variation

CNT diameter variation

Current variation

Threshold voltage variation

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CNT Misalignment

CNT doping variation

Changes effective CNT length

Short between CNTs

Incorrect logic functionality

Reduction in drive current

May not lead to unipolar behavior

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Metallic CNT induced count variation

m-CNT

s-CNT

Excessive leakage current

Increases power consumption

Changes gate delay

Inferior noise performance

Defective functionality

s

-CNT

m

-CNT

Vgs

Current

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Removal of m-CNTFETs

VMR Technique : A special layout called VMR structure consisting of inter-digitated electrodes at minimum metal pitch is fabricated. M-CNT electrical breakdown performed by applying high voltage all at once using VMR. M-CNTs are burnt out and unwanted sections of VMR are later removed.Using Thermal and Fluidic Process: Preferential thermal desorption of the alkyls from the semiconducting nanotubes and further dissolution of m-CNTs in chloroform.Chemical Etching: Diameter dependent etching technique which removes all m-CNTs below a cutoff diameter.

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Overview

MotivationIntroductionCMOS v/s CNTFETsCNT Technology – ChallengesProbabilistic model of faultsModelling performance parameters:ION / IOFF tuning ratioGate delayNoise MarginConclusion

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Probabilistic model of CNT count variation due to m-CNTs

PNgs=ngs|N=n=nCngspsngspm(n−ngs)PNgm=ngm|N=n=nCngmps(n−ngm)pmngm

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Conditional probability after removal techniques

Ns = number of surviving s-CNTsNm = number of surving m-CNTsprs = conditional probability that a CNT is removed given that it is s-CNT prm = conditional probability that a CNT is removed given that it is m-CNTqrs = 1 - prsqrm = 1 -prm

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Overview

MotivationIntroductionCMOS v/s CNTFETsCNT Technology – ChallengesProbabilistic model of faultsModelling performance parameters:ION / IOFF tuning ratioGate delayNoise MarginConclusion

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Effect of CNT count variation on ION / IOFF tuning ratio

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Current of a single CNT

ICNT = ps Is + pmImµ(ICNT) = psµ( Is )+ pmµ(Im )ICNT = drive current of single CNT (type unknown)Is = drive current of single s-CNTIm = drive current of single m-CNTps = probability of s-CNTpm = probability of m-CNT

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Ns = count of s-CNTNm = count of m-CNTIs,on = s-CNT current, Vgs = Vds = VddIs,off = s-CNT current, Vgs = 0 and Vds = VddIm = m-CNT current, Vds = Vdd

 

ION / IOFF ratio of CNTFET

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µ(𝐼𝑂𝑁)µ (𝐼𝑂𝐹𝐹) = 𝑝𝑠 1 − 𝑝𝑟𝑠 𝜇(𝐼𝑠,𝑜𝑛) + 𝑝𝑚 1− 𝑝𝑟𝑚𝜇(𝐼𝑚)𝑝𝑠 1 − 𝑝𝑟𝑠𝜇(𝐼𝑠,𝑜𝑓𝑓)  + 𝑝𝑚 1− 𝑝𝑟𝑚 𝜇(𝐼𝑚)

µ(𝐼𝑂𝑁)µ (𝐼𝑂𝐹𝐹) = µ( 𝑁𝑠) µ(𝐼𝑠,𝑜𝑛  ) + µ( 𝑁𝑚 ) µ( 𝐼𝑚 )µ( 𝑁𝑠) µ(𝐼𝑠,𝑜𝑓𝑓  ) + µ( 𝑁𝑚 ) µ( 𝐼𝑚 )

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Effect of various processing parameters on the ratio µ(ION) / µ(IOFF)

µ(ION) / µ(IOFF) is more sensitive to prmµ(ION) / µ(IOFF) = 104 for prm > 1 – 10 -4 = 99.99 % for pm = 33.33%

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1-

prm

 

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Overview

MotivationIntroductionCMOS v/s CNTFETsCNT Technology – ChallengesProbabilistic model of faultsModelling performance parameters:ION / IOFF tuning ratioGate delayNoise MarginConclusion

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Effect of CNT count variation on Gate delay

 

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= =

 

 

 

 

 

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Plot of v/s

 

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= 0.3

 

 

 

N = 10

N = 20

N = 30

N = 40

N = 50

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Plot of v/s N

 

 

N

0.2

0.4

0.6

0.8

0.9

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Overview

MotivationIntroductionCMOS v/s CNTFETsCNT Technology – ChallengesProbabilistic model of faultsModelling performance parameters:ION / IOFF tuning ratioGate delayNoise MarginConclusion

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Noise Margin of CNTFET

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VIL and VIH

Substituting = Vin, , and = Differentiating with respect to Vin and substituting -1

 

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nFET

p

FET

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For CNTFET,

For CMOS,

V

IL

and V

IH

NM

L

= V

IL

- 0

NM

H

= V

DD

– V

IH

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Overview

MotivationIntroductionCMOS v/s CNTFETsCNT Technology – ChallengesProbabilistic model of faultsModelling performance parameters:ION / IOFF tuning ratioGate delayNoise MarginConclusion

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CONCLUSION

Modeled count variations and hence device current as a probabilistic functionStudied the affect of these faults on tuning ratio and gate delayInferred some design guidelines that could be used to judge the correctness of a processMathematically derived noise margin based on current equations – better noise margin than a CMOS

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