ideas and a first specification draft P Valerio The source of the error pierpaolovaleriocernch 2 The leakage power consumption was calculated using a power measurement on a shift register using the same technology and dividing by the number of flipflops in the chain ID: 549841
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Slide1
ClicPix ideas and a first specification draft
P. ValerioSlide2
The source of the error…
pierpaolo.valerio@cern.ch
2
The leakage power consumption was calculated using a power measurement on a shift register using the same technology (and dividing by the number of flip-flops in the chain)
A little error in reading the plot caused a miscalculation of 3 orders of magnitude…
It’s actually MILLIAMPS!Slide3
… and the updated power budget
pierpaolo.valerio@cern.ch3
Bunch
ON
OFF
ON
Sleep
Analog C[0:N]
ON
Idle
ON
Sleep
Digital C[0]
ReadOut
ON
Idle
ON
Sleep
Digital C[1]
ReadOut
Idle
ON
ON
Sleep
Digital C[N]
ReadOut
Idle
20ms
Pixel Analog
ON
Pixel Digital
ON
Periphery Analog
ON
Periphery Digital
ON
IO LVDS
Pads
OFF
Bunch Train (3.0 W/cm
2
)
Pixel Analog
OFF
Pixel Digital
ON
Periphery Analog
OFF
Periphery Digital
ON
IO LVDS
Pads
ON
Chip Readout (360
mW
/cm
2
)
Pixel Analog
OFF
Pixel DigitalIdlePeriphery AnalogOFFPeriphery DigitalONIO LVDS PadsOFF
Idle (7.8 mW/cm2)
Readout TimeSlide4
4
pierpaolo.valerio@cern.ch
64x64 array (25 microns)
64x64 array (20 microns)
Die area
3 mm
2 mm
Area left for the periphery and pads
Chip
floorplan
1 mm clearance for sensor bonding
Pads
SensorSlide5
Sensor bonding
5The chip will be functionally complete and it will be usable as a tracking detector (although it will have a smaller size and it will lack some automatic controls for debug purposes)
Testing the demonstrator in a beam or with a radioactive source would be ideal to fully test its performances and characterize it
In order to acquire data from a source, a sensor needs to be bonded to the chip. There are some problems in doing it:
The foundry will not give us any full wafer as the project will be implemented in a MPW
The pitch of the bonding is very small. Advanced technologies (copper pillars, indium bumps) will be needed
The pitch can be relaxed if we decide to bond only one every four pixels
pierpaolo.valerio@cern.chSlide6
Pixel logic
6
Each pixel includes simultaneous 4-bits TOA and 4-bits TOT measurements using a reference 100 MHz clock
The clock is distributed along each column exploiting the delays of buffers to give each pixel an “incoherent” clock signal, in order to simplify the clock distribution tree and to avoid a synchronous switch of every pixel in the matrix (which would affect the stability of the power supply)
The readout is on a per-column basis, distributing the full 320 MHz clock (for a DDR bandwidth of 640 Mbps)
A compression logic allows skipping pixels which were not hit during the acquisition. A cluster-based compression is being evaluated
Power saving techniques include clock gating when the pixel is not being read out and power gating (with an external signal) for the analog part when the chip is not acquiring data
pierpaolo.valerio@cern.chSlide7
Shutter
Load_conf
Readout
Poweroff
Analog_bias
To the periphery
Pixel block diagram
7
pierpaolo.valerio@cern.ch
4 bits
TOT
To the pixel above
To the pixel below
Clk
Data
Clk
Data
Mask, TP
Disc_out
Data
Compression logic
Analog Frontend
4 bits
TOA
HF
Enable logic
4 bits tuning DAC
Clock dividerSlide8
Analog pixel electronics
8pierpaolo.valerio@cern.ch
I
KRUM
/2
M
FB1
C
F
C
TEST
M
FB2
M
LEAK
C
LEAK
C
L
I
KRUM
V
out
V
in
I
det
V
FBK
V
dout
C
BUF
g
m
V
th
DAC
V
test
A current DAC provides threshold tuning to calibrate the array
A test capacitor is included to inject test pulses in the frontend
The biasing point can be globally tuned using DACs in the periphery
Bonding PadSlide9
Power pulsing
9
The analog part of the pixel uses too much power by itself.
It’s necessary to implement a controlled power down when the chip is not acquiring data
A preliminary calculation sets the time the analog frontend can be on to be not more than 100
μ
s. In order to be functional, however, the circuits need some time to settle (around 20
μs)In order to make the requirements for the power supply more relaxed, each column can be turned on at a different time to gradually turn on each chip
pierpaolo.valerio@cern.ch
t
Power
Bunch crossing
~15
μ
s
20
μ
sSlide10
Periphery and end-of-column
10A periphery logic with a 14-bit command register will be implemented to control all the features of the chip. This logic will generate control signals for the various parts of the periphery and of the pixel array reading serial commands from an external pin
DACs will be implemented to generate reference voltages. An external absolute voltage reference will be needed due to the lack of a band-gap block
Configuration data (e.g. for calibration) are sent serially to
each
pixel, one bit per column, in order to reduce the speed of the clock in the array
The periphery will also include a block that automatically select which clock signal (if any) will be sent to the pixel array, between the counting clock (used for TOT and TOA measurements) and the readout clock
pierpaolo.valerio@cern.chSlide11
Periphery block diagram
11pierpaolo.valerio@cern.ch
Data_in_column
To next column
Periphery State Machine
Data IN
14-bits command register
DACs (and their
config
registers)
Load_conf
Readout
Readout MUX
Data OUT
Data_out_column
Clock gating logic
Clk_readout
Clk_acquisition
clk
V_bias
Poweroff
Test_pulse
Analog_bias
Shutter
End of column blockSlide12
Available commands
12
Readout data
1, 2, 4 columns or full
chip
Write per-pixel configuration data
1, 2, 4 columns or full
chipWrite global configuration registers
Biasing DACs, timingsReset arrayShutter control
via external pinAnalog poweroff
via external pin
Send analog test pulse
via external pin
(after array configuration)
pierpaolo.valerio@cern.chSlide13
Future plans for the design
13The submission is scheduled for November, so it’s important to finalize the specifications as soon as possible
Analog blocks were already designed for a test chip and they require minor modifications. Digital blocks are being developed
Some blocks (especially in the pixel) are very similar to the
SmallPix
design, resulting in
code and ideas
sharing that can benefit both projectsThis demonstrator lacks a few “standard” blocks, such as a PLL or a band-gap. They are necessary in many projects and, as more and more people start using 65 nm technology, they will become available
pierpaolo.valerio@cern.ch