EET 2261 Unit 9 - PowerPoint Presentation

Slide1

EET 2261 Unit 9Interrupts

Read

Almy

,

Chapters

17 – 19

.

Homework #9 and Lab #9 due next week.

Exam #2 next week.Slide2

An

interrupt

is a mechanism for causing a program to temporarily suspend what it’s doing, and do something else instead.

InterruptsSlide3

Interrupts are commonly used with I/O devices (keyboards, etc.). By using

interrupt-driven I/O

, a program can efficiently service the I/O devices only when they need attention.

The alternative is

polled I/O, in which the program periodically stops what it’s doing and checks to see whether any I/O device needs service.Programming with interrupts is a bit tricky, but it results in more efficient use of the processor’s time.

Interrupt-Driven I/O versus

Polled I/OSlide4

Suppose you’re at home working on a demanding task (writing a paper), and at the same time you’re waiting

for FedEx

to deliver an important package.

Two possible approaches:

Focus on writing your paper, and let the FedEx driver ring the doorbell to announce her arrival. Get up from your desk every 30 seconds to look out the window for the FedEx truck.

An AnalogySlide5

On this analogy:

Your paper-writing task is like

the

processor’s main program.

The FedEx delivery is like an I/O device.The first approach (relying on the doorbell) is like interrupt-driven I/O.

Makes

good use

of your time!

The second approach (getting up from your desk every 30 seconds) is like polled I/O. Not a good way to work, is it?

An Analogy (Continued)Slide6

In real life, there may be many different events that could interrupt you from your primary task:

Doorbell

Telephone

Tornado siren

Dog scratching at the door to be let out

Similarly, the HCS12 has many (about 50) different kinds of interrupts that may require the CPU to temporarily set aside its main task.

Some of these interrupts come from outside

the HCS12 chip,

and some come from circuits on the HCS12 chip itself.

An Analogy (Continued)Slide7

For complete list, see pages 75-76 of the

Device User

Guide

(or the

similar list on page 157 of the book).The list orders interrupts from highest priority to lowest. (Priority comes into play if two interrupts occur at the same time.)

List of InterruptsSlide8

Of the 50-plus kinds of “interrupts,” the three highest-priority ones are more correctly called

resets:

Reset

Clock Monitor Fail Reset

Computer Operating Properly (COP) ResetThe next two highest-priority ones are more correctly called

traps:

Unimplemented Instruction Trap

Software Interrupt (SWI) Trap

The rest are just called

interrupts

. These are the ones we’ll focus on.

Resets vs. Traps vs. InterruptsSlide9

The programmer can choose whether to allow or block interrupts. (But resets and traps cannot be blocked.) If an interrupt is blocked, it will be ignored by the CPU.

We’ll see later that many special function registers hold bits that let the user

allow or block specific

kinds of interrupts.

Two bits in the Condition Code Register (CCR) also play a key role in allowing or blocking

interrupts

….

Allowing or Blocking InterruptsSlide10

Review: Condition Code Register

The CCR is an 8-bit register that contains:

5 flag bits (H, N, Z, V, C)

2 interrupt mask bits (X and I)

STOP instruction control bit (S)Slide11

CCR Bits X and I

The X bit blocks (if X=1) or allows (if X=0) interrupts from the chip’s XIRQ pin.

See

page 25 of

CPU Reference Manual

.

The I

bit blocks (if

I=1

) or allows (if

I=0

)

all other interrupts, including interrupts from

the chip’s

IRQ

pin

.

See

pages 25-26

of

CPU Reference Manual

.Slide12

The

CLI

Instruction

Starting with Lab #7, most of our programs have included a

CLI

instruction near the beginning.

This instruction clears the I bit in the CCR, thus allowing interrupts to occur.

If you omit this instruction, CodeWarrior will have a hard time communicating with the Dragon12 board and you may get error messages that require you to reset the board and restart CodeWarrior.Slide13

Assuming that interrupts are allowed, when the CPU receives an interrupt signal, it sets aside whatever

it is doing and

runs code

called an

interrupt service routine (ISR) or interrupt handler for that specific type of interrupt.

The programmer (that’s you!) must write these ISRs and place them in memory. An ISR is basically a subroutine that gets called automatically when an interrupt occurs.

Interrupt Service RoutineSlide14

For each

type of interrupt,

there is a fixed location in memory

into which the programmer must load the

starting address of the interrupt service routine (ISR).The group of memory locations set aside to hold the starting addresses of the ISRs is called the

interrupt vector table

.

Interrupt Vector TableSlide15

Memory locations $FF00 through $FFFF are reserved for the interrupt vector table.

Figure from page

26 of

Device User Guide

.Location of Interrupt Vector TableSlide16

See Table 5-1 on pages 75-76 of the

Device User

Guide

.

For each type of interrupt, this

table tells

us 5 things:

Information

in Table 5-1

1. The source (name) of the interrupt.

2. The locations in memory where the programmer must store the starting address of the interrupt’s service routine.

3. Whether the interrupt can be masked (blocked) by a bit in the Condition Code Register (CCR).

4. Whether

the interrupt can be

allowed/blocked somewhere other than the

CCR

.

5. Whether the interrupt can be elevated to a higher priority.Slide17

When

the

CPU

receives an interrupt, it follows these steps:

It finishes executing the current instruction.It pushes the contents of PC, Y, X, A, B, and CCR onto the stack, thus saving a snapshot of exactly what the CPU was doing before it was interrupted. It fetches the address of the appropriate interrupt

service routine

(ISR) from the interrupt vector table and places this address in the Program Counter (PC

).

Continues on next slide….

Steps in Executing an InterruptSlide18

…It

sets the I bit in CCR high to ensure

that no

other interrupt can interrupt the CPU while it’s serving the current

one.It fetches and executes instructions belonging to the interrupt service routine.

The

last instruction of the interrupt service routine must be an RTI (Return from Interrupt

).

RTI causes the CPU to pull the original PC, Y, X,

A, B

, and CCR values from the stack, thus restoring the CPU to the state it was in before it serviced the interrupt

.

It then continues to run the code from where it

left off before the interrupt.

Steps in Executing an Interrupt (Continued)Slide19

Many of the bits in the chip’s special function registers are devoted to configuring and controlling interrupts.

Most of the bits in these registers are either

enable bits

, which we set or reset to decide whether we’re allowing interrupts

or flag bits,

which the hardware sets to indicate that an interrupt has occurred. Your interrupt service routine should reset these flags to “clear” the interrupt.

Interrupts and Special Function RegistersSlide20

Your program named Lab07SwitchesToLEDs sat in a “polling loop” that reads the switches and sends the switch values to the LEDs:

Back:

LDAA

PTH

STAA

PORTB

BRA

Back

If the processor has other tasks that it also needs to do, a better way is to use an interrupt to tell us when the switch settings have changed, instead of repeatedly polling

the

switches.

Polling Versus Interrupts for Port HSlide21

Port H has its own interrupt, which can be caused by any of the bits in Port H:

Enabled or disabled by the bits in

PIEH

:

Flag bits are in

PIFH

:

Port H InterruptsSlide22

Unfortunately Table 5-1 has incorrect info in the fourth column (

Local Enable

) on the rows for Port J, Port H, and Port P.

As noted on the previous slide, the name of the register that holds the enable bits for Port H interrupt is

PIEH

. Similarly for Ports J and P, the registers are

PIEJ

and

PIEP.Typos in Table 5-1

PIEH

PIEJSlide23

Programming an interrupt involves several steps on the programmer’s part:

Enable the interrupt (usually by clearing the I bit in the CCR and setting one or more local enable bits).

Write the interrupt service routine (ISR), which is much like a subroutine except it must end with

RTI

, not RTS

.

Place the ISR’s starting address in the appropriate location within the interrupt vector table.

Programming an InterruptSlide24

Example: Programming an Interrupt

Skeleton of code for using Port H interrupt:

Note that this example enables interrupts on only one of the bits of Port H. You might instead need to enable interrupts for several of the Port H bits, or for all of them. Slide25

As part of your

interrupt service routine (ISR

), be sure to clear the flag bit that caused the interrupt. Otherwise, when the HCS12 exits your ISR, the flag bit will still be set and will immediately cause another interrupt.

Strangely, to clear an interrupt flag bit you must write a 1 to it after having read it while it was a 1. (You

don’t write a 0, which is what you might expect).Next slide extends the previous example to include this step.

Clearing the Interrupt Flag BitSlide26

Previous Example With Additional Line to Clear the Interrupt Flag

Skeleton of code for using Port H interrupt: Slide27

We’ve been looking at

the Port

H interrupt. Ports J and P have similar interrupts.

These Port H, J, and P interrupts provide one way to interrupt the HCS12 when an external event occurs.

The textbook refers to these interrupts as “key wakeups.” None

of the other I/O ports (A, B, E, K, M, S, T)

can generate interrupts

.

But two of the HCS12’s other pins, named XIRQ and IRQ, can also generate interrupts. (IRQ stands for Interrupt Request.)

Other External InterruptsSlide28

Review: CCR Bits X and I

Recall from above

that IRQ

interrupts, like almost all other interrupts, are blocked if the Condition Code Register’s

I bit

is equal to 1.

And XIRQ interrupts are

blocked if the Condition Code Register’s

X

bit is equal to 1. Slide29

The XIRQ and IRQ pins are active-low. They’re normally held high, and they generate an interrupt (assuming they’re not masked by the X or I bits in the CCR) when they are pulled low.

X

IRQ and IRQ Pins Are Active-Low

That’s why the

pin diagram

(on page

52 of the

Device User Guide

) calls them

and

, and why our book calls them *XIRQ and *IRQ.

 Slide30

Note also that pin 56 serves double-duty as both the

pin and as Port E’s

bit

0.

Also, pin 55

serves double-duty as both the

pin and as Port E’s bit

1.

Pins Are Shared with Port E

So

if you

want

to use XIRQ and IRQ

interrupts,

you can’t also use

bits 0 and 1 of Port E for general-purpose I/O.Slide31

We’ve been looking at ways in which external events can interrupt the HCS12.

As we’ll see in the weeks

ahead, many of the functional

blocks within the HCS12 chip

itself can also generate

interrupts. This lets these

blocks force the CPU to

temporarily suspend

execution of its current

program and service their

needs.

Internal InterruptsSlide32

Some Advice on Interrupts versus Polling: Advice #1

In

any program, choose

either polling or interrupts

, and stick with your choice. Don’t use both in the same program.

Interrupts tend to be trickier because they require you to manipulate more bits.

Therefore beginning programmers usually

prefer polling.

But polling is usually less efficient because it ties up the processor’s time that could be devoted to other useful tasks.Slide33

Some Advice on Interrupts versus Polling: Advice #2

Be

sure not to enable interrupts

that you’re

not planning to use, or else your program will end up in left field.

That’s because if the interrupt is enabled but you haven’t set up the ISR and the interrupt vector, when the interrupt occurs the processor will branch to whatever random

instruction the interrupt vector happens

to point to.

For this reason, be careful when copy/pasting old code into a new program. Does the code you’re copying enable any interrupts that you don’t need? If so, delete this part of the code.Slide34

Some Advice on Interrupts versus Polling:

Advice

#3

If

you use interrupts in one program and then start working on another program, the interrupts you enabled in the first program may still be enabled when you run the second program.

To

avoid this, press RESET

between

programs. RESET clears all local interrupt enable bits, thus disabling interrupts.Slide35

Some Advice on Interrupts versus Polling:

Advice

#4

Whether

you’re using polling or interrupts, don’t forget to reset flags after they get set.

Forgetting to do this is a common mistake. If you make this mistake, you’ll get into an endless cycle of handling the same event over and over again.Slide36

Some Advice on Interrupts versus Polling:

Advice

#5

If you’re not sure whether your program is ever getting to a certain point when it runs, use a breakpoint.

Example: Not sure whether the program ever gets to your interrupt service routine? Before

you run the

program, set a breakpoint on the

first instruction

in the service routine.