Blackhawk Emulation ECHNI CAL RT ICLE Using the Adaptive Clocking Feature of the TI OMAP Platform Adding OM AP Adaptive Clocking s upport to TI JTAG Emula ors BHadaptiveClocki ngTA June Using the PDF document - DocSlides

Blackhawk Emulation ECHNI CAL RT ICLE Using the Adaptive Clocking Feature of the TI OMAP Platform Adding OM AP Adaptive Clocking s upport to TI JTAG Emula ors BHadaptiveClocki ngTA June    Using the PDF document - DocSlides

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a nd Blackhawk E A Technologies Inc Adding Ad aptive Clocking Support to TI JTAG Emulators Wha is Ada tive Clo cki ng Adaptive clockin is a feature of sy hesizable cores introduced b ARM Ltd and adopted TI in their OMAP platform wherein th input te ID: 22895

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Blackhawk Emulation ECHNI CAL RT ICLE Using the Adaptive Clocking Feature of the TI OMAP Platform Adding OM AP Adaptive Clocking s upport to TI JTAG Emula ors BHadaptiveClocki ng-TA-01 June 2005
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2 Using the Adaptive Clocking Feature of the TI OMAP™ Platform By Fadata Ltd. a nd Blackhawk – E A Technologies, Inc. Adding Ad aptive Clocking Support to TI JTAG Emulators Wha is Ada tive Clo cki ng? Adaptive clockin is a feature of sy hesizable cores, introduced b ARM® Ltd. and adopted TI in their OMAP platform, wherein th input test clock (TCK) is dela ed (s chronized) fore producing the resulting output clock (RTCK . During this sy nch onization period the target core samples Test Data In (T DI), Test Mode Select (TMS), a nd T K th the core clock. Emulators can a dapt to th e R output of these adaptive clocking cores using a simple scheme. This scheme requires the emulator to gene rate t next T K edg e onl y after receiving an “acknow ledge ” signal from the target, indicating that it has r ceived and processed the previous edge. Th e targ et ill “acknow led ge” th ese TCK edges b repea ting them (after som dela ) on its RTCK outpu t. This protocol creates a nat ural, target controlled “throt tle” for the T K rate. A positive side-effect to this mecha ism is that an dela s intr duced b the JT AG cable a e automatically tak en into consideration. Internall , th e ad aptive clocking mechanism is implemented as a multi-stage sy nch onizer consisting of se veral D-Trigge rs (Figure 1 sy nch onizing the TCK to the core clock of the target (as ll a transferring all other JTAG signals to the core clock domain). T number of s hronizers, Ns, is device- dependent, but has shown to be a value of 3 or 4 in OMAP cores at this time. RTCK is the output from th e last D-trigger a is ty pically connected to th e TCK_RE T pin of the JTAG connector. The theo retical maximum T K rate can be easily calculated as the f equenc y of the cor clock divided by 2 times Ns (Equa tion 1). Handling adaptive clocking is no t obligator so emulators tha do not sup port i should still operate. Th ill, in general, just disregard the information o the RT CK pin. The d back of not using ada pt ive clocking ill be the inabilit of the emulat or to rk at the optimum TCK rate. If t he emulator supports a varia le TCK, t he use ill have to manuall set th e maximum and sustainable TCK fre quenc y t rough e pe rime ntation. And if the device s core has a variable clock rate, this RTCK can change during op eration. Another disad antage for fixed T K emulators is t hat the ill have trouble sy nch onizing t he data t he adaptive clocking cores. For e ample, if the emulator has a 12 MHz TCK and the OMAP core is 24MHz, ou’ll lik ely have data corr uption. Utiliz ing this featur e adds convenience, stability and increased pe rform nce, and is therefor e strongl y desired. The Inver ter Appro ach The simplest so lution is to have the emulator invert each RTC edge to p odu ce the next TCK edge (Figu e 2). The main advantage of this approach is it s ability to reach a T r te very close to the theoretical m ximum. The do side, ho ver, is that the design is fully dep endant on the ta rget ret rn clock and ca nnot function th n on-ad aptive clocking targets. This is because such ta rgets usually hav e TCK_RET shorted to T K on their JTAG connector, forcing the inver er to p oduce an unusable TCK (“infinite T K problem”). The Trigger Inverter Ap pr oach A solution to the nfinite T K problem is to have the emulat or send the t rg et an inverted version of RTC as done in the inverter approach, but o ly afte r sampling it w th it s own clock, referr ed to here as E CK (Figu e 3) . T is method ill make the emulator function w th no n-adaptive clocking targets, but the max mum output TCK w ill be determined b E CK. In this approac h, the sampling of RTCK is best perform ed a du al-edge D-Flip Flop (DF ) to avoid halving the fre uenc of the resulting TCK, w ich ould confuse those emulators that m easure it. Due t the added dela imposed b the DFF, th e maximum K r te ill be somew at low but ill stil l be compatible th non -adapti e clocking targets, ich is its major advanta ge. The as ynchron ous relationship bet en ETCK and t he ta rget core clock introduces an inevitable jitter on the produce TCK. This jitter (w ith a ma ximum value of 0. 5TETCK ) is harmless, and has the ad ded benefit of introducing spread-spectrum m odulation to TCK, lo ring EMI levels and improving EMC. JTAG Emulator Implementa tion We implemented both designs using Blackhaw k JTAG em ulators (models USB510 and US B560) and teste them on a
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TI OMAP5 912 p ocessor w th a ARM926EJ- S core running a 192, 96, 48 and 12 MHz as the adaptive clocking target. The emulators had their TCK- lated logic (contained in a 7-ns Xilinx C olrunner™ o Coolrunne r II CPLD) en hanced to accommodate t he adaptive K support. These units have total del ay , tD = 15 ns (logic dela of 13 ns an d line dela of 2 ns). The maximum TCK for the OMAP5912 running at 192 MHz should have been fCORE/6, or 32 MHz, but on a ccounting for the logic and lin e delay s, rec lculated the actual maximum fTCK of OMA 5912 to be 19.2 MHz. The In er proac produce a jitter-free TCK at 12 M z. The Trigg r-I rter pr oach also produced a 12-MHz TCK along w th the expected jitter. Ho ver, this design functioned cor ectl w th non-adaptive clocking targets, achi eving similar ma ximum TCK freq uencies as non-adapt ive clo cking emulators. Adap ter Boa d Implementation We also implemented the tri gger-inverte r approach in a c mmercially avai lable add-on adapter board (B lackhaw k Adapti e TCK) th at enables adaptive clocking for an TI JTAG emulator lacking this capability (Fi gure 4). The adapt er boa rd is simply inser ed bet een the standar d 14-pin connecti on of th e emulator and tar get boar d and its operation is completely tran sparent to th e emulator. Figure 5 sho s the fundament al logic of the adapter. Since fast low voltage CMOS (LV ) logic w used for this implementation, the emulator reaches TCK f equenc ver c ose to the OMAP5912’s th eoretical maxim m of 19.2 MHz. The characteristic jitte r was also present. Th e a dapter bo ard al so functions correctl th n on-Adaptive T K targets at frequencies as high as 64 MHz. As seen in Figur e 5, the add-on a dapter boa rd also addresses a test reset ( RST) issue found th XDS510™-class emulators built around the SN74ACT89 90 Test Bus Controller ( BC) and certain OMAP targets. This includes t he TI XDS510 ISA card emulator. The issue app ears in emulators that are dependent on th e TBC device and use one of its pins to han dle the TRST signal. The problem occurs w some OMAP targets (e.g. OMAP DM 320) stop their RTCK signal the moment TR ST is asserted. Since the TBC is cloc ked RTCK, it w ill halt, keeping TRST asserted indefinitely nd producing deadlock. The adapte boa rd solves this condition b con necting the emul ator’s TCK to TCK_RET du rin assertion of TRST. This feature of the a dapter bo ard d s not affect emulators that do not use a TBC pin to handle the TRST signal, such as the XDS560™. Timing Analysis Figure 6 sho s TCK (uppe r waveform) and RTCK (lo vefo rm) on an adaptive clocking target being de bug ged b an emulator that does not support adaptive clocking. As the diagram show s, the emulator-supplie d TCK is not adapted to the target R CK sp eed requir ment s, forcing the latter to miss some of its edges. Figure 7 sho s the correct oper ation, w ich s achieved b attaching the sa me emulator used in Figure 6 to the same target, but using an adaptive clocking add-on board. Now the TCK is throttle b R CK t meet the requirements of t he target. Conclu sion Maximum JTA per formance and data integrit on t ’s TI OMAP platform is subject to handling the adaptive clo cking feature of t hese cores. The ad aptive clocking feature allow fo automatic setting of the optimal TCK rate in the sy stem un de r test. How ve r, support for this highly usefu feature is lacking in JTA emulators for TI DSPs currently on the market. Our g oal s to correct this deficiency both directl incorp orating the adapt ive clocking logic into Bla ckh aw k™ J AG e ulators and developing a add-on b oard that allow non-adaptive clocking emulators to handle adaptive clockin , thereb y p ese ving current investments. itten by: Boycho Kostadinov, Ivailo Kassam kov, a nd Nenko La rov, Fadata Ltd nt ri on by Andrey Kostov, F adata Ltd. Andrew Ferr ari, E A Technologies, Inc. Blackhaw k 123 Gaithe r Driv e Mount Laur el, NJ 08054-17 01 3 Web: www .blackhaw k- dsp.com

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