RTL performance verification June 4 2014 DaeSeo Cha Infrastructure Design Center System LSI Division Samsung Electronics Co Ltd Current Performance Verification System Architecture Specification ID: 476178
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Slide1
Using emulation for RTL performance verification
June 4, 2014
DaeSeo Cha
Infrastructure Design Center
System LSI Division
Samsung Electronics Co., Ltd.Slide2
Current Performance Verification
System Architecture Specification
System
Requirement
RTL Integration
FPGA
Architectural Performance Exploration
SystemC
model, real workload aware performance analysis
Architectural Performance Verification
System C model Inaccuracy
Post-Silicon
RTL Performance Verification
Sub-system only Capacity
RTL Performance Verification Full chip Too late in development stage
RTL Performance Verification
Subsystems/full chip using logic simulation
SlowSlide3
New Approach for Performance Verification
System Architecture Specification
System Requirement
RTL Integration
FPGA
Post-Silicon
UVM Testebench
log
log
log
log
GUI Analysis Environment
(PRISM)
Accurate
Cycle Accuracy
Fast
100X+
Early Stage
RTL freeze
Big capacity
Full chip
Fast Analysis
Correlation/Compare
Summary
* PRISM: Samsung In-house Tool
Fast and Accurate Performance VerificationSlide4
Environment Reuse existing UVM simulation environment without any modification Add PV(Performance Verification) components
PV components
Monitor: Collect various performance metrics
Traffic Generator: Random or replay RTL IP’s traffic
Performance Verification Platform Slide5
UVM Co-emulation Environment
UVM Architecture for Co-emulation
Simulation environment
Incremental elaboration having primary, incremental snapshot
Building test scenarios by combining
testbench
and design in full-chip
Emulation environment
DUT runs in emulator, incremental elaboration scheme used in emulator
prim_top
sw_top
Interface
Sequence
Test scenario
Module
Virtual sequencer
REG2BUS adapter
Register predictor
Register Model
AXI
bus
Bus
UVC
Interface
Interrupt
hw_top
tb_top
UVM testbench
Simulator
DUT
Emulator
DUT
Incr_top Slide6
Performance Monitor -1/2Performance MetricsLatency: Min/Max/Average, time-varying, accumulated, distributed
Bandwidth
: Min/Max/Average, time-varying, accumulated, distributed
Utilization: Min/Max/Average, time-varying, accumulated, distributed Address pattern
Response timeCustomized metrics like IP’s internal signals (FIFO level) ImplementationSynthesizable code for both simulation and emulationCollect performance metrics on AXI interfaceIssueRun-time overhead in emulation Synchronization overhead between emulator and simulator
Log file
PRISM
PM
PM: performance monitorSlide7
Performance Monitor – 2/2ExperimentsPV results should be recorded in-orderMany experiments are done to reduce run-time overhead
GFIFO
Transactions are collected in order, it is congruent with the SW simulation
Parallel execution of monitor transaction in SW Improve performance
bit a; bit [5:0] b; int c; function void my_mon(bit x1, bit [5:0] x2, int x3); $fdisplay(“%d %d %d”, x1, x2, x3);
endfunction; initial $ixc_ctrl("gfifo", “my_mon"); always @(clk) begin my_mon(a, b, c) end
bit a; bit [5:0] b; int c; always @(clk) begin $fdisplay (“ %d %d %d”, a, b, c);
end
Method
Description tbcall sync
Overhead No PV MonitorBaseline 398
-$displaySync with TB
using $fdisplay()32,798
81XGFIFOBuffering monitored transactionCollecting process in back ground
4721.12XSimulation Monitor
GFIFOSlide8
Performance Analysis Environment PRISM (Perfor
mance V
is
ualization System)
Charting PV results in GUIEasy to find a performance issue by viewing PV results in a single GUI Slide9
Experimental ResultApplicationMultimedia test scenarios such as video playback, camera recording
Run-time speed
+100x faster than simulation
Bugs found
Critical bugs and design weak points which would not been detected during simulation-based verificationSlide10
ConclusionPV using emulator is a mainstream solutionVery f
ast bring up
using UVM Co-emulation
Reusing UVM full-chip testbench
without any modificationPV in early design development stage with cycle accuracy +100x faster speed compared with simulation approachEfficient PV analysis by PRISMFuture WorkAdd more features to PRISM - correlation, smart PV report etc. Develop ACE PV Monitor for dealing with cache-coherencyDeploy UVM Co-emulation for other test scenarios Slide11
Thank you