Samyoung Bang Kwangsoo Han Andrew B Kahng and Mulong Luo Presented By Siddhartha Nath Outline Introduction and Related Works CrosstalkAware Layout Optimization ID: 469739
Download Presentation The PPT/PDF document "Delay Uncertainty and Signal Criticality..." is the property of its rightful owner. Permission is granted to download and print the materials on this web site for personal, non-commercial use only, and to display it on your personal computer provided you do not modify the materials and that you retain all copyright notices contained in the materials. By downloading content from our website, you accept the terms of this agreement.
Slide1
Delay Uncertainty and Signal Criticality Driven Routing Channel Optimization for Advanced DRAM Products
Samyoung Bang#, Kwangsoo Han‡, Andrew B. Kahng‡† and Mulong Luo†Presented By: Siddhartha NathSlide2
OutlineIntroduction and Related Works
Crosstalk-Aware Layout OptimizationTestcase GenerationExperimental Setup and ResultsConclusionsSlide3
Introduction
DRAM interconnect channelsNarrow and long interconnect channel large crosstalkManual design is still the dominant methodology might be far from optimal
…
Aggressor
Victim
A
n
automated DRAM channel
layout
optimizer
is essential
to
minimize the crosstalk
effectsSlide4
Related Works
Crosstalk-aware analysisAnalytical modeling of crosstalk-induced delay and noise [Xiao00] Arrival time alignment of aggressor and victim for worst-case victim delay and noise [Gross98, Sato00] Crosstalk-aware designSwizzling-based interconnect design to reduce crosstalk-induced delay
and
noise [Yu09]
Crosstalk-aware MILP-based detailed routing
[
Gao93]
No existing works integrate accurate
c
rosstalk
-aware analysis
and automated design!Slide5
Our Contributions
Develop an accurate closed-form analytical delay calculatorPropose several methods to achieve high-quality, scalable channel layout optimization MILP-based segment optimizationPair-swapping segment optimizationAchieve 29% reduction of maximum weighted delay uncertainty compared to the conventional signal permutationSlide6
OutlineIntroduction and
Related WorksCrosstalk-Aware Layout OptimizationTestcase GenerationExperimental Setup and ResultsConclusionsSlide7
Track 1
Track 2Track 3Track 4Segment 1Segment 2Segment 3Segment 4Segment |G|
…
Track |T|
…
…
Problem Statement
Inputs:
Long and narrow rectangular channel
set of
tracks
T
Set of segments
G
; set of signals
S
Criticality classes (e.g., CLK signal
highest criticality)
Design rules (e.g., pitch, width, spacing) for each class
Inter-buffer length for each class
Objective: minimize max weighted delay uncertainty among all signals in different
classesSlide8
Problem ComplexityExhaustive
search solution space size: E.g., 4 signals, 4 tracks, 4 segments 244
= 331776
Segment-by-segment optimization:
E.g., 4
signals, 4 tracks, 4
segments
24
4 = 96
Pessimistic assumption
: following segments are not coupled (i.e., distance between signals are infinity)
Track t
0
Track t
1
Track t
2
Track t
3
Track t
4
Track
t
|T
|-1
…
…
…
…
…
Segment g
0
Segment g
1
Segment g
2
Segment g
3
Slide9
Segment-by-segment Optimization
RC network of two neighboring tracksDistance ↑
↓
↑
delay uncertainty
↑
Sample example
400um channel,
C
c
= 2.7fF/
seg
.,
C
g
= 8fF/
seg
.,
R
d = 300
Ω,
CL
= 20fFSuboptimality of segment-by-segment optimization: 0.4%
Optimal
Max delay uncertainty: 7.16ps
Segment-by-segment
Max delay uncertainty: 7.19ps
Signal permutation
Max delay uncertainty:
9.57psSlide10
Overview of Crosstalk-Aware Layout
OptimizationTestcase specifications: channel length and width, #signals, #tracks, etcSegment-by-segment optimizationMILP-based segment optimizationPair-swapping segment optimizationAccurate and fast delay uncertainty calculator
Pair-swapping
s
egment optimization
MILP-based
s
egment optimization
Optimized layout with min delay uncertainties of signals
Testcase
specifications
Segment-by-segment optimization
Delay Uncertainty CalculatorSlide11
MILP-based Segment Optimization: Notations
Variables below are calculated using our delay uncertainty calculator delay uncertainties of signal at the input of each segment: estimated delta delay uncertainty of signal
when signal
is its neighbor at the current segment
Variable below is an input of
testcase
specification
: weight of class
of signals
Variables below are outputs of the optimizations
: binary indicating assignment of signal
onto track
: binary indicating if signal
and
are neighbors
Slide12
Basic C
onstraints for Our MILPFor each signal , it occupies exactly one track: For each track , it can be occupied by at most one signal:
If signal
and signal
are on track
and track
, then signal
and signal
are neighbors
+
+
+
For segment with |S| tracks, there will be at most |
S
|
-1 pairs of neighbors
Slide13
Track t
0Track t1Track t2
Track t
3
Track t
4
Track
t
|T
|-1
…
…
…
Segment
g
j
Segment g
j+1
MILP-based Segment Optimization
Estimation of delay uncertainties
Enumerate all the combinations of pairs of signal
and signal
signal
.
The delta delay uncertainty of signal
at the end of the segment is
The objective:
minimize
)
Signal 1
Signal 2
Signal 3
Signal 4
Slide14
Decomposition for Scalability
Limitation of MILP-based method scalabilityDecompose tracks into set of subsets Solve MILP instance for each subsetOffset half of the subset size to mix signals Track t1Track t2Track t3Track t|T|-1…
…
…
…
…
Segment g
0
Segment g
1
Segment g
2
Segment g
3
|V
0
|=V
|V
1
|=V
|V
2
|=V
|V
3
|=V
|
V
r
|
V
|V
1
|=V
|V
2
|=V
|V
3
|=V
|V
0
|=[V/2]
|V
r+1
|
V
|V
0
|=V
|V
1
|=V
|V
2
|=V
|V
3
|=V
|
V
r
|
V
|V
1
|=V
|V
2
|=V
|V
3
|=V
|V
0
|=[V/2]
|V
r+1
|
V
Slide15
Overview of Crosstalk-Aware Layout Optimization
Testcase specifications: channel length and width, #signals, #tracks, etcSegment-by-segment optimizationMILP-based segment optimizationPair-swapping segment optimizationAccurate and fast delay uncertainty calculatorPair-swappingsegment optimization
MILP-based
s
egment optimization
Optimized layout with min delay uncertainties of signals
Testcase
specifications
Segment-by-segment optimization
Delay Uncertainty CalculatorSlide16
Pair-swapping Segment Optimization
Main idea: swap the signal with maximum weighted delay uncertainty with other signalsProcedure:Step1: Sort all the signals in increasing order of delay uncertaintiesStep2: Swap the signal w/ max weighted delay uncertainty and min weighted delay uncertaintyStep 3: Revert the swap if no improvementStep 4: Repeat Steps 1, 2 until no weighted delay uncertainty improvement 70ps30ps
Track t
1
Track t
2
Track t
3
Segment g
1
Segment g
2
4
0ps
4
0ps
4
0ps
40ps
4
0ps
4
0ps
45ps
60psSlide17
Overview of Crosstalk-Aware Layout
OptimizationTestcase specifications: channel length and width, #signals, #tracks, etcSegment-by-segment optimizationMILP-based segment optimizationPair-swapping segment optimizationAccurate and fast delay uncertainty calculator
Pair-swapping
s
egment optimization
MILP-based
s
egment optimization
Optimized layout with min delay uncertainties of signals
Testcase
specifications
Segment-by-segment optimization
Delay Uncertainty CalculatorSlide18
Delay Uncertainty Calculator
SPICE simulation is accurate long runtimeFast closed-form delay uncertainty calculatorGiven aggressor-victim pair, generate noise waveform induced by crosstalk using 2- circuitMeasure the impact of noise on delayDynamic delay change of victim signal Delay Change CurveCalculate delay uncertainty using DCC
Layout and electrical
information of any
aggressors and victims
Noise waveform
modeling using
2-
circuit [Cong01]
Noise waveform
to Delay Change
Curve (DCC) [Sato03]
Delay Calculator
Delay uncertainty
induced by crosstalkSlide19
Accuracy of Delay Uncertainty Model
Comparison of our model and the model in [Gupta04] Testcase: five signals, five tracks and 8000um channel divided into 8 segments Randomly generate 300 swizzling patterns 1500 data points Rank correlation between our model and SPICE Rank correlation between [Gupta04] model and SPICE[Gupta04] P. Gupta and A. B. Kahng, “Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling”, Proc. VLSI Design, 2004, pp. 431-436.
Rank of delay uncertainty by our model
Rank of delay uncertainty by SPICE
1500
1000
500
500
1000
1500
Max rank difference: 148
Rank of delay uncertainty by [Gupta04]
Rank of delay uncertainty by SPICE
1500
1000
500
500
1000
1500
Max rank difference: 487Slide20
OutlineIntroduction and Related
WorksCrosstalk-Aware Layout OptimizationTestcase GenerationExperimental Setup and ResultsConclusionsSlide21
Testcase Generation: General Inputs
No public benchmark for DRAM channel routing optimization develop testcase generatorGeneral inputsChannel lengthChannel widthNumber of signalsNumber of tracksNumber of segmentsProbability that a signal in class 0 is correlated with a signal in class 1Supply voltageClock period
class
0
class
1
class
2
class
3
class
4
class 0
1
1
1
0.8
0.5
class
1
1
1
0.8
0.5
0.5
class 2
1
0.8
0.5
0.5
0.5
class
3
0.8
0.5
0.5
0.5
0.5
class
4
0.5
0.5
0.5
0.5
0.5
…
Channel length
Channel
width
Signals
Tracks
SegmentSlide22
Testcase Generation: More Inputs
Class-specific inputsNumber of signals Ground capacitance (Resistance)Coupling capacitance between two signals in different classesDistances between any two consecutive buffersInput capacitance (Output resistance) of bufferSignal-specific inputsLoad capacitanceInput resistanceInput slewActivity correlation with other signals
Load cap.
Input
resistance
Input slew
Signal 1
class 0
Signal 2
class 1
Input cap.
Output res.
Distance
Signal 1 Slide23
OutlineIntroduction and Related
WorksCrosstalk-Aware Layout OptimizationTestcase GenerationExperimental Setup and ResultsConclusionsSlide24
Experimental Setup
Channel length = 8000umPitch, width, space and buffer location of each classSignal-specific inputs: Rd = 500Ω, tslew = 130ps, Cload = 4fFExperiment 1: Impact of number of signals and tracks
Experiment 2:
Impact of
percentage of
signals
in each class
Experiment 3: Impact of correlation of signals
Experiment 4: MILP vs. pair-swapping vs. signal permutation
Class
Pitch (um)
Width (um)
Space (um)
Buffer location
0
1.1
0.4
0.7
Per 1000um
1
1.0
0.3
0.7
Per 1000um
2
0.7
0.21
0.49
Per 2000um
3
0.51
0.2
0.31
Per 4000um
4
0.38
0.19
0.19
No bufferSlide25
Experiment 1: Impact of Number of Signals and Tracks
Vary number of tracks and signals Weights of classes = {10, 6.7, 4, 2, 1}Same number of signals in each classTestcase E1T1 resultSignals in higher-criticality class smaller delay uncertaintyMost critical two signals mostly on the boundary of channel
Testcase
#signals
#tracks
E1T1
10
10
E1T2
10
11
E1T3
10
12
E1T4
20
20
E1T5
20
21
E1T6
20
22
Signal
0
class
0
Signal
1
class
3
Signal
2
class
1Signal3
class4Signal
4 class2
Signal5
class4Signal6
class1Signal7
class3Signal8
class2
Signal9
class0
Class 0
Class 2
Class 3
Class 4
Class 1Slide26
Experiment 2: Impact of Percentage of
Signals in Each ClassNumber of tracks = 20 and Number of signals = 20Change the percentage of signals in each criticality classSame weights used in Experiment 1Observation% of lower-criticality signals ↑ objective ↓Replace higher-criticality signals to lower-criticality signals
maximum weighted delay uncertainty
↓
Testcase
Priority of class A
Priority of class B
#signals
in class A
#signals
in class B
D
max
A
D
max
B
Objective
E2T1
0
1155
96.1109.2
961
E2T201
101090.5
108.5905
E2T3
015
1582.8107.5
828
E2T402
1010
88.2141.1
882
E2T503
101085.0
186.4850
E2T60
410
1084.0215.5
840Slide27
Experiment 3: Impact of Correlation
of SignalsNumber of signals = 5 and number of tracks = 5Two testcases: E3T1 and E3T2Four signals higher-criticality class One signal lower-criticality classE3T1: signals in different classes are fully correlatedE3T2: signals in different classes are not correlatedObservation
Orange colored signal (
lower-criticality
class) in E3T2
routed in the middle of channel
minimize max weighted delay uncertainty
Delay uncertainty of signals: E3T1
>
E3T2
Layout of channel for E3T1
Layout of channel for E3T2Slide28
Max weighted delay uncertainty
for testcases T2 – T5 Runtime of MILP and pair-swappingfor testcases T2 – T5MILP vs. Pair-Swapping vs. Signal Permutation
(2)
Scalability evaluation with larger
testcases
Size of decomposition subset of
MILP:
20
Testcases
T2 – T5
T2: #tracks = 100, #signals
for each class =
{15, 40, 30, 10, 5}
T3: #tracks
=
110
,
#signals
for each class =
{15, 40, 30, 10, 5}
T4: #tracks
= 200
, #signals for each class =
{30, 80, 60, 20, 10}
T5: #tracks =
220, #signals
for each class = {30, 80, 60, 20, 10}Observation
Pair-swapping achieves better
results than signal permutation
Up to 29%
max weighted
delay uncertainty reduction
Empty tracks (10% of #tracks)
Up to 19.9%
max weighted
delay uncertainty reduction
Runtime: pair-swapping < MILP
19.9%
29%Slide29
OutlineIntroduction and Related
WorksCrosstalk-Aware Layout OptimizationTestcase GenerationExperimental Setup and ResultsConclusionsSlide30
Conclusions
Propose a DRAM routing channel optimization to specifically target the layout design of long, resource-constrained channels in modern DRAM productsOptimizer is signal criticality-aware, and minimizes a maximum weighted delay uncertaintyAchieve up to 29% reduction of maximum weighted delay uncertainty compared to a traditional track permutation methodologyOngoing workFlexible buffer locationUse of invertersSlide31
AcknowledgmentsWork supported by Samsung ElectronicsSlide32
Thank
You!