denotes the specifications which apply over the full operatingtempera - PDF document

L denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. VS = ±7.5V, fCLK = 1MHz, R1 = 10k, C1 = 10pF, TTL or CMOS clock inputlevel unless otherwise specified.Note 2: For tighter specifications please contact LTC Marketing. PARAMETERCONDITIONSMINTYPMAXUNITS /2kHz Output Voltage Swing andVOperating Input Voltage RangeV Total Harmonic DistortionV at 1kHz0.015% at 1kHz0.03% Wideband NoiseV5V, Input = GND 1Hz to 999kHz1507.5V, Input = GND 1Hz to 999kHz165 Output DC OffsetV50175mV50125mVOutput DC Offset TempCoV5VÐ100 1020k Output Impedancef= 10kHz2 Output Short-Circuit CurrentSource/Sink3/1mA Clock Feedthrough200V Maximum Clock Frequency50% Duty Cycle, V7.5V5MHz Power Supply CurrentV1022mA 5V1223mA26mA = 1MHz1628mA32mA Power Supply Voltage Range Ð15Ð30Ð45Ð60Ð75Ð9010100 S = ±5VTA = 25°CfCLK = 1MHzfC = 10kHz ± 0.1dBfÐ3dB = 10.7kHz TYPICAL PERFOR A CE CHARACTERISTICS Gain vs FrequencyPhase vs FrequencyGroup Delay 01356Ð45Ð90248711 S = ±5VTA = 25°CfCLK = 1MHzfC = 10kHz 01236789121011 S = ±5VTA = 25°CffC = 10kHz L operation both pins should be tied to one half supply(Figure 2). Also Pin 8 and Pin 10, although they are notinternally connected should be tied to analog ground orsystem ground. This improves the clock feedthroughperformance.+, VÐ (Pins 4, 12): The V+ and VÐ pins should bebypassed with a 0.1µF capacitor to an adequate analogground. Low noise, nonswitching power supplies arerecommended. To avoid latchup when the power suppliesexhibit high turn-on transients, a 1N5817 Schottky diodeshould be added from the V+ and VÐ pins to ground(Figure 1).INV A, R(h, I) (Pins 7, 14): A very short connectionbetween Pin 14 and Pin 7 is recommended. This connec-tion should be preferably done under the IC package. In aUUbreadboard, use a one inch, or less, shielded coaxial cable;the shield should be grounded. In a PC board, use a oneinch trace or less; surround the trace by a ground plane.NC (Pins 8, 10): The Òno connectionÓ pins preferablyshould be grounded.fCLK (Pin 11): For ±5V supplies the logic threshold level is1.4V. For ±8V and 0V to 5V supplies the logic thresholdlevels are 2.2V and 3V respectively. The logic thresholdlevels vary ±100mV over the full military temperaturerange. The recommended duty cycle of the input clock is50% although for clock frequencies below 500kHz theclock ÒonÓ time can be as low as 200ns. The maximumclock frequency for ±5V supplies is 4MHz. For ±7V sup-plies and above, the maximum clock frequency is 5MHz.Do not allow the clock levels to exceed the power supplies.For clock level shifting (see Figure 3).Figure 1. Using Schottky Diodes to Protectthe IC from Power Supply SpikesFigure 2. Single Supply Operation. If Fast Power Upor Down Transients are Expected, Use a 1N5817Schottky Diode Between Pin 4 and Pin 5.Figure 3. Level Shifting the Input T2L Clock�for Single Supply Operation, V+ 6V.Figure 4. Buffering the Filter Output. The Buffer Op AmpShould Not Share the LTC1064-1 Power Lines. L213 FFFFV + VÐV+ POWER SOURCE 10k10k1064 F04 RECOMMENDED OP AMPS:LT1022, LT318, LT1056COMP2*ÐfNCNCINV CVIN+ INV AVIN LTC1064-1121413V+ µF 5k 2.2k 5k 5k1µFT2LLEVELV+R(h, I)COMP2*VÐfNCNCVIN+VIN 213V+VÐ F F1N5817 ÐfNCNCINV CVIN+INV AVIN TC1064-1121413V+= 15V0V TO 10V1064 F02 0.1µF 0.1µF 5k 5kV+COMP2*VÐfCLKNCVOUTNCINV CVINAGND+AGNDVOUTVIN TYPICAL APPLICATIO S (Pin Numbers Refer to the 14-Pin Package) L However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. OBSOLETE PACKAGE .045 Ð .065(1.143 Ð 1.651) .100(2.54)BSC .014 Ð .026(0.360 Ð 0.660) .200(5.080)MAX .015 Ð .060(0.381 Ð 1.524) .125(3.175) (7.62 BSC).008 Ð .018(0.203 Ð 0.457)0° Ð 15° 234 (5.588 Ð 7.874) 118 .025(0.635)RAD TYP NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE (0.508)MIN .120(3.048)MIN .130 ± .005(3.302 ± 0.127) .045 Ð .065(1.143 Ð 1.651) .065(1.651)TYP .018 ± .003(0.457 ± 0.076) .005(0.125)MIN ± .015*(6.477 ± 0.381) .770*(19.558)MAX3124567891011121314 (0.203 Ð 0.381) (7.620 Ð 8.255) .325+.035Ð.015+0.889Ð0.3818.255 1. DIMENSIONS AREINCHESMILLIMETERS*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) .100(2.54)BSCS16 (WIDE) 0502 NOTE 3 .398 Ð .413(10.109 Ð 10.490)NOTE 4 1514109 .037 Ð .045(0.940 Ð 1.143) .004 Ð .012(0.102 Ð 0.305) .093 Ð .104(2.362 Ð 2.642) .050(1.270)BSC .014 Ð .019(0.356 Ð 0.482)TYP ° Ð 8° TYP NOTE 3 .009 Ð .013(0.229 Ð 0.330) .005(0.127)RAD MIN .016 Ð .050(0.406 Ð 1.270) .291 Ð .299(7.391 Ð 7.595)NOTE 4 × 45°.010 Ð .029(0.254 Ð 0.737) INCHES(MILLIMETERS)NOTE:1. DIMENSIONS IN 2. DRAWING NOT TO SCALE3. PIN 1 IDENT, NOTCH ON TOP .420MIN RECOMMENDED SOLDER PAD LAYOUT123N/2 .050 BSC.030 TYP SW Package16-Lead Plastic Small Outline (Wide .300 Inch)(Reference LTC DWG # 05-08-1620) L APPLICATIO SFEATURESTYPICAL APPLICATIO Low Noise, 8th Order, Clock , Elliptic Antialiasing FilterFrequency ResponseÐ15Ð30Ð45Ð60Ð75Ð90040 5152535 8th ORDER CLOCK SWEEPABLE LOWPASS ELLIPTIC ANTIALIASINGFILTER MAINTAINS, FOR 0.1Hz f 10kHz, A ±0.15dB PASSBAND RIPPLE AND 72dB STOPBAND ATTENUATION AT 1.5 × fTOTAL WIDEBAND NOISE = 150µVIN = 1V TC1064-112 0.1µF 0.1µF Antialiasing Filters
Telecom PCM Filters