PPT-TRILL DC Interconnect

draftbalajil2vpntrilloveripmultilevel02txt Balaji Venkat Venkataswami Ramasubramani Mahadevan Shivakumar Sundaram Narayana Swamy Perumal Bhargav Bhikkaji DELLForce10 Architecture Considered. 9 10 11 12 13 12481632 Performance normalized to 1MB LLC size MB 04 06 08 10 0 64 128 192 256 Percore Performance normalized to 1 core Number of cores 64 128 192 256 0 64 128 192 256 Chip Performance normalized to 1 core Number of cores brPage 4br br brPage 1br Clarinet Trill Chart T 123 123 T 123 123 T 123 123 F T 123 F 123 T 123 F 123 T 123 123 F T 123123 T 123 123 T 123 F 123 T 123123 F T 123 F 123 G T 123123 G T 123 . Hao. Yizhou. Li. Donald Eastlake . Analysis of Active-Active connection solutions. . draft-hao-trill-analysis-active-active-01. March 2014. 1. Introduction. Trill Campus. RB1. RB2. RB3. CE1. CE2. Badrish Chandramouli , Jonathan Goldstein , Mike Barnett, Rob ert DeLine, Danyel Fisher, John C. Platt , James F. Terwilliger, John Wernsing Microsoft Research 1 {badrishc, jongold, mbarnett, rd Proposal. Bob Ross, . Teraspeed. Labs. bob@teraspeedlabs.com. EPEPS 2015 IBIS Summit. San Jose, CA, October 28. , 2015. Draft Presented September 2, 2015 at the Interconnect Working Group. Copyright 2015 . draft-eastlake-trill-rbridge-bfd-00.txt. Donald E. Eastlake 3. rd. 155 Beaver Street. Milford, MA 01757 USA. <d3e3e3@gmail.com>. November 2010. 1. TRILL OAM & BFD. Vishwas. . Manral. IP Infusion. Radia Perlman. radiaperlman@gmail.com. 1. November 2013. Don’t we have “appointed forwarders”?. November 2013. 2. R1. R2. R3. R1, R2, and R3 can all forward. DRB assigns work, based on VLANs. But requires R1, R2, R3 all carefully coordinated, all see all packets. DESIGN. - PROF. RAKESH K. JHA. . CORPORATE . INSTITUTE OF SCIENCE & TECHNOLOGY , BHOPAL. DEPARTMENT OF ELECTRONICS & COMMUNICATIONS . Chips are mostly made of wires called . interconnect.. Wires are as important as transistors. . Requirements. Chen Zhao, Frank Yang. NetApp, Inc.. Storage Interconnect Requirements. Multi-destination RMA operation with reliable unconnected transport. 2. www.openfabrics.org. Storage Interconnect Requirements. Through Communication-Based Design. Veronica . Eyo. Sharvari. Joshi. System on chip. Overview . Transition from Ad hoc System On Chip design to Platform based design. Partitioning the communication design into layers using the “network on chip” approach. OAM. IEEE . 802.1 Meeting . San Diego. July . 16. th. -20. th. , 2012. b. y. Tissa Senevirathne. Donald Eastlake 3. rd. Objective. Explore complementary . OAM. model between IEEE 802.1 and . IETF. /TRILL. November 2013. 1. Updates. Requirements document is now RFC 6905. Framework document cleared WG last call.. Fault management document is a WG document. Performance management document adopted as WG document. David Mohabir. University of Arizona. March 19. th. , 2012. Testing and diagnosis of interconnect faults in cluster-based FPGA architectures. Section 1. Motivation. Quickly identify faulty components. Radia. Perlman . Fangwei. . Hu. Donald Eastlake 3rd . Kesava. . Vijaya. . Krupakaran. . Ting Liao. Problem statement. 2013-11-5 Tuesday. 2. Smart Endnode. RB1. RB2. RB3. E1. E2. E3. SW 1. TRILL Campus.