NMOS Dfferential Pair Verylike but not quite your assignment The Schematic DxDesigner Drawing Startup Set bias current Set cascode Differential pair and current Output stage and load ID: 1031054
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1. A MOSFET Opamp with an N-MOS Dfferential PairVery-like but not quite your assignment
2. The Schematic: (DxDesigner Drawing)Startup Set bias current Set cascode Differential pair and current Output stage and load bias voltage mirror
3. Device Parameter Estimates from SPICEelementmodelvdsvgsvthvovidgmrom1nssb0.7480.8510.5470.3043.77E-052.90E-045.54E+05m10nssb3.3680.8510.5470.3044.12E-053.11E-048.09E+05m12nssb0.7110.7110.5460.1653.51E-055.01E-045.05E+05m13nssb0.8380.8510.5470.3043.79E-052.91E-045.92E+05m14nssb3.0781.0790.8400.2393.51E-053.27E-048.12E+05m15nssb1.0921.0920.8360.2563.79E-053.31E-046.32E+05m18nssb0.0231.9300.5591.3715.36E-063.42E-064.34E+03m2nssb3.1560.7520.5470.2051.89E-052.22E-041.36E+06m20nssb3.9290.0230.594-0.5717.88E-124.17E-131.00E+12m3nssb3.0890.7520.5470.2051.89E-052.22E-041.36E+06m9nssb1.6540.8510.5470.3045.63E-054.29E-045.19E+05 m11pssb0.4781.6320.7460.886-4.1E-056.34E-052.13E+04m11apssb1.1541.1540.7930.362-4.1E-052.08E-046.64E+05m16pssb1.0721.0720.7370.335-3.5E-051.92E-047.27E+05m17pssb3.0701.0720.7270.344-3.8E-051.99E-047.14E+05m19pssb4.9773.0700.7812.289-5.4E-064.35E-069.43E+07m4pssb0.5121.0480.8120.236-1.9E-051.42E-048.52E+05m5pssb0.5791.0470.8120.235-1.9E-051.42E-049.19E+05m6pssb0.5841.0960.7410.355-1.9E-059.73E-051.09E+06m7pssb0.5851.0960.7410.355-1.9E-059.73E-051.10E+06m8pssb3.3461.1640.7260.437-5.6E-052.35E-045.96E+05Parameter Table for MOSFET Opamp Example
4. Setting the Bias CurrentYou don’t have to do this. I give you a current source for your assignment. This is one way to separate the amplifier bias from the exact VDDM16 and M17 are a conventional current mirror with the input side on the left. M12 and M13 are a modified mirror with input on right and output on the left.M12 is 4X wider than M13, probably made by parallel connection of 4 copies of M13. Notice that the body of M12 is connected to the source, not to ground (VSS).ID13 times R is the difference in the overvoltages of M12 and M13. Equating ID13 to ID12 and using KVL, we have:This has two solutions: both current and VOV13 are zero orThis means that
5. Starting Up the Bias & Providing Cascode BiasThe inverter has a very low gate threshold voltage so its output is only high when the bias voltage is too low.M20 forces current into the top mirror until the output bias voltage is enough to settle to a final value.M10 matches M13 so it is a current source with the same standard value as M13. The current ID10 sets VGS for M11 & M11A (effectively a single transistor) that is used to bias the cascode current mirror.
6. Output Stage at Low FrequencyCommon Source AmplifierOutput load impedance from Channel Length Modulation (r0) in M8 and M9 together with the load and parasitic capacitancesLoad resistance =Gain proportional to the transconductance of M8 Pole at output: f = ??
7. First Stage: NMOS Differential Pair with Cascoded Current MirrorOutput current gain is the transconductance of one of the differential pair transistors (2.22e-4 sie).The current mirror output impedance is the same problem as the Widlar source and the exam problem. The differential pair output resistance is just r0 for one of the differential pair transistors (1.36e6 ohms.)Node impedance is essentially r0 of M3.Gain is
8. Transfer Function with RM = 0Second pole Miller effect Dominant poleZero – Bad for phase!!!
9. Transfer Function with RM in PlaceZero term bad for phaseZero – New term good for phase Make RM > 1/gm
10. Where Are the Poles?Denominator polynomial is a quadratic polynomial for which the zeros are:Using a Taylor series approximation:Pole frequencies show “splitting” – first pole is lowered and second pole is raised from positions without feedback:
11. What Is the Slew Rate?This circuit has a classic differential input pair (M2 and M3) for high CMRR and low DC drift.It also has a current mirror (M4 – M7) with bias from the drain current of M1: IM1Q = 38 μamps.A large step input puts all 38 μamps into the Miller capacitor CM = 5.5 pf for S.R. = 6.9 V/ μsec.VDDiin = IM1Q-A0IM1QIM1QvOUTIM1QCM
12. Final Performance SpecificationsAmplifier PropertyValueA0 – DC Gain86 DB (X20,000)fp – dominant pole position400 HzfGBW8.0 MHzfU – unity gain frequency5.6 MHzOutput stage resistance at low frequency 277 KZero position10.7 MHzSlew Rate V/secOutput stage quiescent current65 aOpamp quiescent current103 aBias circuit quiescent current104 aTotal system quiescent current210 aVDD5.0 voltsTotal system power1.1 mWPhase margin = 60 deg.