ARCHITECTURE 1 Agenda Introduction Partial Reconfiguration Basics Design Considerations Advantages of Partial Reconfiguration Challenges of Partial Reconfiguration Application Examples ID: 360868
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PARTIAL RECONFIGURATION USING FPGAs: ARCHITECTURE
1Slide2
AgendaIntroductionPartial Reconfiguration BasicsDesign ConsiderationsAdvantages of Partial Reconfiguration
Challenges of Partial Reconfiguration
Application Examples
Case Study
2Slide3
Introduction
Basic Premise :
Hardware
reconfiguration is allowed during execution of
an application.
FPGA Chip
Design A
Design B
Design C
Some Interesting Applications
Dynamic
Instruction Set
Architecture
Software
Defined
Radio
Video
encoding
techniques
Cryptography
Networking protocols
3Slide4
IntroductionClassification of FPGA with respect to configuration capabilities
Dynamic Partial Reconfiguration : Reconfiguring only a part of the device at run time while the rest of the device executes.
Useful for systems which can time share the FPGA resources.
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IntroductionArea reductionPower reductionHardware ReuseFlexibilityPerformance Improvement
Higher Level of Parallelism
Time sliced resource sharing
Fast system startLoad a basic module to enable a fast system boot upLoad peripheral modules later.Smaller bitstreams
sizes
Application Portability
Encapsulation of reconfigurable system into a portable
application.
Benefits5Slide6
Partial Reconfiguration Basics
Each
vendor’s
products can have different characteristics and
utilities
Some common terminology are as below.
TERMINOLOGY
Reconfigurable Partition(RP)
Dynamic Partial Reconfiguration (DPR)
Reconfigurable Module (PRM)
Configuration Memory (CM)
Frames
Partial BitstreamMerged BitstreamStatic Logic (Base Region)Bus Macro
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Partial Reconfiguration Basics
Overall Structure
CLBs – Configurable logic blocks
IOBs – Input-output buffers
DSP48s – Xilinx’s digital signal processing units
BRAMs – Block Random Access Memories
FIFOs – First-in First-out buffers
DCMs – Digital Clock Managers
Structure Overview
CLBs
IOBs
DCMs and Clock Dist.
DSP48s
BRAMS and FIFOs
Figure 1. Virtex-4 LX15 FPGA layout
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Partial Reconfiguration BasicsStructure Overview
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Partial Reconfiguration BasicsBit Stream and Frames
FPGAs are reprogrammed by writing bits into CM
Organized in small blocks called ‘Frames’
Multiple
frames
required
to program
a
column of
tiles(After Virtex
II )Contains both routing and logic tile configuration.
Virtex-6 Frame size: 81 x 32 bits (81 words)Typical Bit streams for Virtex-6 are in the range of 43Mb to 190 Mb
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Partial Reconfiguration Basics
Different columns of
FPGA fabric
can have different bit
streams
PR
overhead for full flexibility
Possible to reduce Bit stream Size :
- Compression Techniques - Partial ReconfigurationBit Stream10Slide11
Partial Reconfiguration BasicsRow address – 0 to 9 Top/Bottom row – with respect to HCLK Together with row address can locate the tile Major Address : Columns 0 onwards
Minor Address : No. of frames in tile
Block type : Logic Blocks, BRAMs, Routing Blocks.
Frames
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Partial Reconfiguration BasicsBus Macros: Means of communication between PRMs and static designAll connections between PRMs and static design must pass through a bus macro with the exception of a clock signal
Type of Bus Macros
Tri-state buffer (TBUF) based bus macros
Slice-based (or LUT-based) bus macros
Bus Macros
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Partial Reconfiguration BasicsUsed for connecting points to link Static and reconfigurable partIntroduced in 2002Fixed positions on the FPGA fabric Present along a thin vertical slice Extra hardware required. No longer supported in modern FPGAs.
Xilinx Bus Macros (Tri state Buffer Based)
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Partial Reconfiguration Basics
LUTs and Switch matrix acts as the connection points (2004)
Passes the boundary of static and reconfigurable regions in a predefined manner.
Uses 2 LUTs per wire
Increased latency and area
Not used any more.
Partition Pins replace Bus Macros
Xilinx Bus Macros (LUT Based)
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Partial Reconfiguration Basics15Partition Pins are the logical and physical connection between static logic
and reconfigurable
logic
.Automatically created for all RP ports.Also referred to as Proxy LUTs.
It is single LUT1
No special instantiations required
Not Bidirectional
Partition PinsSlide16
Externally Serial configuration portJTAG (Boundary Scan) portSelect Map port
Internally
Though the Internal configuration access port (ICAP)
using an embedded microcontroller or state machine
Partial Reconfiguration Basics
Methods of Reconfiguration
Summary
of Configuration Options
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Partial Reconfiguration Basics
Reconfiguration via a processor
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Partial Reconfiguration Basics
Port to read and write the FPGA configuration at run
time
Enables
a user to write software programs for an embedded processor that modifies the circuit structure and functionality during the circuit’s operation
.
Allows for automated runtime reconfiguration
ICAP Interface
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Partial Reconfiguration Basics
Storage Device
Bus System
DMA to Storage Device
Read back Support
Configuration manager
ICAP Interface
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Design Considerations Partitioning style could be island styleSlot BasedGrid Based
Partitioning Style
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Design ConsiderationsPartitioning style affects placement and flexibilityA partition defines the smallest atomic area a module can be assignedIsland style – suffers from fragmentation
Slot style
- also suffers from fragmentation but to a lesser extent. Offered by the current vendors Xilinx and Altera.
Grid Style – Reduced fragmentation. Difficult to support.To enhance flexibility, the PR module must be placed and routed in every region it needs to be configured.Additional stress on Bit stream size.
Placement Flexibility
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Design ConsiderationsColumn wise layout of different logic primitivesMust be considered when placingDepending on the type of logic primitives used by the module(SLICEX, SLICEM, etc), relocation may or may not be possible.
Resource
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Design ConsiderationsOne of the potential advantages of PR – Power reductionBut PR itself requires power.Power during PR is spent in: 1. Configuration Data Access –
- Spent on the configuration controller
- Off/On chip Memory access - Programming interface(ICAP, SelectMAP,etc)
2. Actual configuration of FPGA Resources
Power
Bonamy
, R., et al. "Power Consumption Models for the Use of Dynamic and Partial Reconfiguration."
Microprocessors and Microsystems
(2014).23Slide24
Design ConsiderationsTasks switching power graph T1
T2 and T2T1
Power
Bonamy
, R., et al. "Power Consumption Models for the Use of Dynamic and Partial Reconfiguration."
Microprocessors and Microsystems
(2014).
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Module-based PR:Implement any single component separately.Constrain components to be placed at a given location.Complete bitstream is finally built as the sum of all partial bit streams.
Difference-based PR:
Implement the complete
bitstreams separately.Implement fix parts + reconfigurable parts with components constrained at the same location in all the bitstreams.
Compute the difference of two bitstreams to obtain the partial bitstream needed to move from one configuration to the next one.
Design Considerations
Design Flows
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Design Considerations
Module Based P-R
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Design ConsiderationsUseful for making small on-the-fly changes to design parameters such as logic
equations, Filter Parameters.
Procedure
:Designer makes small logic changes using FPGA_Editor
:
changing I/
Os
, block RAM contentsLUT programming
muxsflip-flop initialization and reset valuespull-ups or pull-downs on external pinsblock RAM write modesChanging any property or value that would impact routing is not recommended due to the risk of internal contentionUses BitGen to generate a bitstream that programs only the difference between the two versions. Very quick switchingDifference Based P-R
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Design Considerations
Difference Based P-R
LUT equations change
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Changing BRAM contentsDesign Considerations
Difference Based P-R
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Challenges of Partial Reconfiguration
Complicated
design
flow
Manual assistance for reconfiguring different target devices.
Security
issues
Decrease performance as compared to full
configuration.Xilinx reports 10% degradation in clock frequency when using PR.
Xilinx PR Implementation Flow
HDL Design Description
HDL Synthesis
Set Design Constraints
Placement Analysis
Implement Static Design and PR Modules
Merge
Final Bitsreams
Manual steps
30Slide31
Complete Architecture Overview
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Application examples of Partial ReconfigurationEvolution ArchitecturesArtifical Neural NetworksEvolvable Hardware PlatformsFuzzy systems
Modular Robotics
Speed Up
Crypto (Asym)Area SavingNetworking (exchange packet filters according to traffic)Modulation/frequency/encryption hopping in military
radios
Digital Signal Processing
JPEG Encoder/Decoder systems
Edge detection applications
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Case StudyFault tolerant ProcessorIF ,MAC and ALU are the PRMsDifferent configurations
available for each module.
Focus on the self healing
feature more than the performance itself.
Fault Tolerance – Self Healing Architecture
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Case Study
Reconfigurable Crypto processor
Processor can choose from
Different crypto algorithms
Major Area savings
Some Power Savings too.
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Case Study Fast Start up is a 2 step configurationUseful in time critical systems to initiate a swift system start up.
Example :
Automotive safety
Fast Start Up
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Thank you Questions ? 36