Vishwani D Agrawal vagrawalengauburnedu 1172012 ITC 12 Elevator Talk 1 Support from NSF Grant 1116213 Effects of Reducing Supply Voltage Critical path slows down Power reduces as V ID: 582887
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Slide1
Reduced Voltage Test Can be Faster!
Vishwani D. Agrawalvagrawal@eng.auburn.edu
11/7/2012
ITC '12: Elevator Talk
1
Support from NSF Grant 1116213Slide2
Effects of Reducing Supply Voltage
Critical path slows down.Power reduces as V2.Test produces more than functional activity; consumes more power that the circuit is designed for.Test clock is slower due to power constrain.
11/7/2012
ITC '12: Elevator Talk
2Slide3
Power and Frequency vs. Voltage
11/7/2012ITC '12: Elevator Talk
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Voltage VDD
Max.
c
lock frequency
(structure constrained)
Peak power/cycle during test
PMAXfunc
Nominal
voltage
Vtest
Power constrained
t
est
Structure
constrained
testSlide4
Reduced Voltage Test Results
Circuit (180nm CMOS)
PMAX per cycle (
mW
) 1.8V test freq.
(MHz)
Test voltage (volts)
Test clock freq. (MHz)
Test time reduction (%)
s298
1.2
187
1.08
500
62.5
s13207
21.3
110
1.45
165
40.3
s38584
110.61291.5018731.011/7/2012ITC '12: Elevator Talk
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P. Venkataramani and V. D. Agrawal, “Reducing Test Time of Power ConstrainedTest by Optimal Selection of Supply Voltage,” Proc. 26th International Conf.VLSI Design, January 2013.