PPT-Memory and Addresses CS/COE

0447 Jarrett Billingsley Class announcements btw if you look at the notes alongside each slide there are often answers to questions I ask and other extrafun info repeat after me loads copy from . Goals for Today. Protection: Address Spaces. What is an Address Space?. How is it Implemented?. Address Translation Schemes. Segmentation. Paging. Multi-level translation. Inverted . page tables. Virtualizing Resources. Basic Concepts. Lecture for CPSC 5155. Edward Bosworth, Ph.D.. Computer Science Department. Columbus State University. The Memory Component. The memory stores the instructions and data for an executing program. Instruction Sets. 10.1 Instruction Characteristics. 10.2 Types of Operands. 10.3 Data Types. 10.4 Operators. 10.1. Machine Instruction Characteristics. Machine Instruction Characteristics. Machine Instructions- are instructions executed by the processor.. Operating Systems. CS550. Memory Manager. Memory . manager - manages allocation and . de-allocation . of main . memory. Plays significant impact on operating system . because it is. . so important to . Goals for Today. Protection: Address Spaces. What is an Address Space?. How is it Implemented?. Address Translation Schemes. Segmentation. Paging. Multi-level translation. Inverted . page tables. Virtualizing Resources. Architecture. CPU . Processing units. Caches. Interrupt controllers. MMU. Memory. Interconnect. North bridge. South bridge. PCI, . etc. PC Architecture. Address Spaces. Translation from logical to physical addresses. Cornell CS 3410. Calling Conventions. int. . gcd. (. int. x, . int. y) {. . int. t, a = x, b = y;. while(b != 0) {. t = b;. b = mod(a, b);. a = t;. }. return a;. }. How many caller/. Use main memory as a “cache” for secondary (disk) storage. Managed jointly by CPU hardware and the operating system (OS). Programs share main memory. Each gets a private virtual address space holding its frequently used code and data. Addressing. Architecture. CPU . Processing units. Caches. Interrupt controllers. MMU. Memory. Interconnect. North bridge. South bridge. PCI, . etc. PC Architecture. Early Memory (un)management. A history of the x86. However, smallest addressable unit is a Byte (8 bits). . bit 7 6 5 4 3 2 1 0. . . msb. . lsb. Most computers permit access of memory through words (16 bits, 32 bits or 64 bits). Background. Swapping . Contiguous Memory Allocation. Segmentation. Paging. Structure of the Page Table. Example: The Intel 32 and 64-bit Architectures. Example: ARM Architecture. Objectives. To provide a detailed description of various ways of organizing memory hardware. Managed jointly by CPU hardware and the operating system (OS). Programs share main memory. Each gets a private virtual address space holding its frequently used code and data. Protected from other programs. Background. Contiguous Memory Allocation. Paging. Structure of the Page Table. Swapping. Example: The Intel 32 and 64-bit Architectures. Example: ARMv8 Architecture. Objectives. To provide a detailed description of various ways of organizing memory hardware. CPU . Processing units. Caches. Interrupt controllers. MMU. Memory. Interconnect. North bridge. South bridge. PCI, . etc. PC Architecture. Early Memory (un)management. A history of the x86. Simple layout with a single segment per process.