Measuring Progress and Value of IC Implementation Technolog - PowerPoint Presentation

Slide1

Measuring Progress and Value of IC Implementation Technology

Andrew B. Kahng, Hyein Lee and Jiajia Li UC San Diego VLSI CAD Laboratory (“ABKGroup”)http://vlsicad.ucsd.edu Slide2

Measuring Progress and Value

Systems, and system design, are rapidly evolvingCloud, biomedical, autonomous cyberphysical, …Non-von Neumann, quantum, nano-crossbar based, neuromorphic, …Beyond-CMOS next switches, storage elements, interconnects3D/heterogeneous integration paradigmsDesign automation (DA) = Glue for progress made at different levelsThis talk: How can we measure the progress and value of DA ?

Define R&D objectives



Clarify

credit to and

value of EDA technologySlide3

ITRS Design Cost Model

ITRS Design Cost Model quantifies

notional, required progress

and value of IC implementation technology

Without innovations after 2000, SOC design = $1B in 2013

Without innovations after 2013, SOC design = $3.4B in 2028Slide4

Call to Action: Design Capability Gap

Measure to Improve: measuring progress enables definition of targets for future progress“Design capability gap” (2013 ITRS report) between available vs. realized density scaling Design capability scaling gap since ~2007Slide5

QOR (%)

Design time (weeks)

Current (130, 100)

#3

#2

#1

(30, 100)

(130, 120)

(105, 130)

(50, 110)

(30, 90)

#3. Optimized back-end

(mixed-height/-library floorplan/placement; ultimate place and route, power / clock distribution)

#2. Modeling, signoff criteria

(tightened BEOL corners; reduced

guardband

; AVS-aware signoff)

#1. Bespoke, design-specific flow

(predictive, one-pass flow, optimal tool usage)

30

130

90

100

Call to Action:

I

so

-QOR Schedule Reduction

A MOONSHOT !!!Slide6

This Talk

To “(re-) open the discussion” regarding the feasibility of progress and value assessments for lower-level, “tactical” design technologyWhat should be assessed?Is assessment feasible?Can we build up to higher-level assessments?Example assessments of progress and value of IC implementation technologyTracking of EDA tools’ performance across versions

Upper bound on value

from future

technologies

Systematic, “universal” ranking of design enablement

Means

to measure value, progress

of academic tools Slide7

Assessing Progress and Value: Examples

Assessing EDA Tool ProgressBounding Future ProgressRank-Ordering of Design EnablementsMeasuring Academic Progress and ValueSlide8

Assessing EDA Tool Progress

EDA marketing gives us “year-on-year” snapshots  “4X speedup”, “10% QOR improvement”, …(Note: composition of press releases does not give a long-term picture of design technology evolution)Must comprehend long-term trajectoriesShow how tools evolve to handle new technologiesProject future requirements for EDA tools Show the values of EDA technology innovationsWe demonstrate “longitudinal” studies of EDA tool performance across multiple versionsP&R tool, signoff STA toolSlide9

Example Longitudinal Study: P&R Tool

Experimental setupVersions = {v10, v12, v14, v15} (released between 2010 and 2015)Design: VGA (32K~76K instances)Power and timing results are reported using Tempus v15.2Denoised with clock period +1ps, -1psP&R flowMCMM optimizationPower meshClock tree synthesis (CTS)Pre-/post-CTS optimization; post-route optimization (with hold)Slide10

Three technologies: 28LP, 45GS and 65GPArea/power improves across versions

Large number of design rule violations for 28LP with v10, v12Improved understanding of 28nm pin access and local routing congestion in matured toolsP&R Result Comparison

(Results are normalized to v15)

Improved area

Improved power

Large #DRVSlide11

Performance of P&R

VersionsIn general, runtime and memory usages are comparable across tool versionsv12 runtime is exceptionally high for 28LP(Results are normalized to v15)Slide12

Example Longitudinal Study: Signoff STA Tool

Experimental setupVersions = {v9, v10, v11, v12, v13, v14, v15, v16} (released between 2009 and 2016)Design: LEON3MP with 28LP (462K instances)#analysis modes = {2, 4, 8, 16, 32}Averaged power is used for power analysisClock pessimism removal (CRPR, CPPR) is enabledTiming results∆Setup slack ≤ 73ps, ∆ hold slack ≤ 549psReason: different default constraint (PI-to-register paths) and different path delay calculation methodPower results are almost the same across versionsSlide13

Performance of Signoff STA Versions

Earlier versions use less memoryv14 shows the minimum runtimeOf course, these are anecdotal – but what if an “Underwriters Lab” were to assess progress more systematically?(Results are normalized to v16)Slide14

Assessing Progress and Value: Examples

Assessing EDA Tool ProgressBounding Future ProgressRank-Ordering of Design EnablementsMeasuring Academic Progress and ValueSlide15

Bounding Future Progress

Benchmarks with known optimal or “good” solutions  Lower bounds on heuristic suboptimalityPEKO/PEKU: Placement, w/ know-optimal solution and known upper bounds on wirelengthEyechart/[Kahng12]: Gate sizing, w/ known-optimal solution [Hagen95]: Partitioning, placement, w/ known-good solutionsWhat about upper bounds on benefits from given technologies (e.g., 3DIC)? Guide R&D objectives and prioritizationsSlide16

Upper Bounds on 3DIC Benefits

3DIC is promising in “More-than-Moore” eraMany works estimate power benefits from 3DICs[Chan16] proposes the concept of implementation in “infinite dimension”  upper bounds on 3DIC power and area benefitsSlide17

Implementation in Various Dimensions

Infinite dimension: Netlist optimization with zero wireload modelKey idea: Infinite dimension gives us a bound on what three dimensions can deliver

3D (w/ N tiers):

Placement and routing with shrunk LEF (by 1/

) and annotated TSV RC

Best 2D:

Conventional implementation: vary key parameters

 Select best solution

Parameters = synthesis frequency/utilization, placement utilization, BEOL options

Pseudo-1D:

Placement and routing with large layout aspect ratio (e.g., 10:1)

 Slide18

Infinite-Dimension Bound on 3D Power Benefits

CORTEX M0JPEG

Iso-performance power comparison among implementations in different dimensions

Gaps between infinite dimension vs. 2D



M

aximum 3D benefits

= 36% and 20% for CORTEX M0 and JPEG

36%

20

%

clock period (ns)

clock period (ns)

infDSlide19

Infinite-Dimension Bound on 3D Area Benefits

Iso-performance area comparison among implementations in different dimensions3D integration offers very small (< 10%) area benefits over 2D 3D integration may have converted area benefit into power benefit (e.g., buffer sizing or duplication)

3D (2 tier)

3D (3 tier)

3D (4 tier)

CORTEX M0

JPEG

clock period (ns)

clock period (ns)

10%

10%

infDSlide20

Assessing Progress and Value: Examples

Assessing EDA Tool ProgressBounding Future ProgressRank-Ordering of Design EnablementsMeasuring Academic Progress and ValueSlide21

PROBE

PROBE: Placement, ROuting, Back-End-of-line Measurement UtilityRank BEOL stack options with respect to routing capacity with various routers (Rj), placers (Pk), and netlists (Nh)Evaluate routers / placersSlide22

Key Methodologies in PROBE

Main challenge in generating testcases (placements) = Hard to “control difficulty” of testcases Our approach: Gradually perturb the initial placement by swapping adjacent cells More perturbation = more difficult testcasesIntuitively, a “pair-swap” is an appropriate quantum of placement suboptimality

input

output

net

Routing difficulty ↑

Swapped cells

Flyline changed by cell swapsSlide23

Metric to Measure Routing Capacity

Higher routing capacity?  A BEOL stack option can sustain more perturbed placements #DRC vs. perturbationEach BEOL stack option has a different trend K thresholdAmount of random perturbation where #DRC explodesMeasured as #swaps normalized to total #cellsMetric for routing capacityHigher K threshold = higher routing capacity

BEOL1_6 = 4

BEOL2_6 = 11

BEOL3_6 > 15

BEOL0_6 = 0

#swaps

#DRCSlide24

Comparison of Various Design Enablements

Four design enablements shown here Combinations of placements (mesh, real-P1, real-P2) and two routers (R1 and R2)Observe “universal” rank-ordering of BEOL stack options across different design enablementsSuggest possible “rank-ordering” of placers and routersR2 > R1 (mesh-R1 vs. mesh-R2)(P1, R1

) > (P

2

, R

2

) (real-P

1

-R

1

vs. real-P

2

-R

2

)

B

1

B

2

B

3

B

4

B

5

mesh-R

1

mesh-R

2

real-P

1

-R

1

real-P

2

-R

2

N

2

N2

N

2

N2

Name

Rank

#1X

#1.5X

#2X

B

1

4

3

0

4

B

2

4

2

3

2

B

3

2

3

3

0

B

4

1

4

0

2

B

5

3

5

0

0

<BEOL stack option>Slide25

Assessing Progress and Value: Examples

Assessing EDA Tool ProgressBounding Future ProgressRank-Ordering of Design EnablementsMeasuring Academic Progress and ValueSlide26

Measurement of Academic Progress and Value

Mismatches in data models, benchmark formats, technology files, etc. High barrier to assessing academic tools’ progress and valueLower the barrier: horizontal benchmark and benchmark extension [Kahng14] (GLSVLSI14)  Maximize “A2A” assessment across benchmarks, technologies and tools



Better targets for academic research



Faster technology transfer into real-world practice

A2A benchmark

generation

methodology, scripts applied

to support

ICCAD15

placement contest

(

http://cad-contest.el.cycu.edu.tw/problem_C/default.html

)Slide27

Scope of Horizontal Benchmark Extension

Maximized “apples-to-apples” assessmentBenchmarks: ISPD11 (placement), ISPD12/13 (sizing), real designsTechnologies: ISPD12/13, foundry 28/45/65/90nmSlide28

Formats and Libraries

CAD Tools require different input formatsBookshelf formats (academic) vs. DEF/LEF (commercial)Solution: Use a converter and scriptsDifferent libraries across technologiesMissing technology files (e.g., missing LEF in ISPD12/13)Solution: Artificial LEF generationExtract cell/pin area of X1 cell from reference technologyScale cell/pin area for larger cellsGranularity of libraries differ across technologiesSolution: Match granularity with timing/power table interpolations

Technology

file

Liberty (timing/

power)

Technology file

Liberty (timing/

power)

LEF generation

Granularity

matchingSlide29

Enablement of Sizing Assessments

Benchmark transformation: P&R to sizingMissing logic function / timing information (e.g., ISPD11)Solution: Gate mapping Determine sequential cells from width / pin count / #blocks w/ same widthRandomly map standard cells based on widths and pin countsSome academic sizers require complete timing graphSolution: Attach floating nets to portsGenerate additional ports if necessary based on Rent’s rule

Sizing-oriented benchmark

Geometry information

Netlist

w/

parasitics

P&R-oriented benchmark

Geometry information

Netlist

w/

parasitics

Gate

mappingSlide30

Sizer Assessment (Across Technologies)

Academic sizer achieves better solution in ISPD technology, but worse solution in foundry technolgies Possibility that academic sizer is specialized to the ISPD technology

Benchmark:

netcardSlide31

Sizer Assessment (Across Tools)

Academic sizers achieve smaller leakage, but have larger timing violation and larger runtime Indicate potential improvements for academic sizers

Technology: ISPD

Benchmark:

netcardSlide32

Conclusions

Examples of “assessing progress and value”Longer-range longitudinal assessmentsUpper bounds on future progress“Universal” rank-ordering of design enablementsA2A: connect academic research to industry context Just scratching the surface  many possibilities!Getting back to “progress and value”Open up commercial EDA tools to benchmarkingDevelop meaningful, scalable, unified benchmarks and metricsEstablish an “Underwriters Laboratories” for EDA

Assess costs of, and provide solutions to, non-interoperabilitySlide33

THANK YOU !

UCSD ABKGroup is grateful to Qualcomm, Samsung, NXP, ASML, the IMPACT+/C-DEN centers, Mentor Graphics and the NSF for research support. We thank IMEC and Cadence for additional research enablements and collaborations.