Design of Airthmetic circuits and code converter using K-map Half and Full Adder, Half and Full Subtractor, Gray to Binary and Binary to Gray Code Converter (up to 4 bit) Airthmetic Circuits: (IC 7483) Adder Subtractor, BCD Adder
"Design of Airthmetic circuits and code converter" is the property of its rightful owner. Permission is granted to
download and print the materials on this website for personal, non-commercial use only, and to display it
on your personal computer provided you do not modify the materials and that you retain all copyright
notices contained in the materials. By downloading content from our website, you accept the terms of this
agreement.
Presentation Transcript
01
Design of Airthmetic circuits and code converter using K-map Half and Full Adder,
Half and Full Subtractor,
Gray to Binary and Binary to Gray Code Converter (up to 4 bit)<br>
02
Airthmetic Circuits: (IC 7483) Adder & Subtractor, BCD Adder Encoder/Decoder: Basics of Encoder, decoder, comparison, (IC 7447) BCD to 7- Segment decoder/driver. Multiplexer and Demultiplexer: Working, truth table and applications of Multiplexers and Demultiplexers, MUX tree, IC 74151 as MUX, DEMUX tree, DEMUX as decoder, IC 74155 as DEMUX Buffer: Tristate logic, Unidirectional and Bidirectional buffer (IC 74LS244 and IC 74LS245)<br>
03
3 bit binary to gray code converter<br>
04
Working of n-bit parallel Adder firstly the full adder FA1 adds A1 and B1 along with the carry C1 to generate the sum S1 (the first bit of the output sum) and the carry C2 which is connected to the next adder in chain.
Next, the full adder FA2 uses this carry bit C2 to add with the input bits A2 and B2 to generate the sum S2(the second bit of the output sum) and the carry C3 which is again further connected to the next adder in chain and so on.
The process continues till the last full adder FAn uses the carry bit Cn to add with its input An and Bn to generate the last bit of the output along last carry bit Cout.<br>
05
N-bit parallel adder<br>
06
N-bit parallel subtractor<br>
07
Working of n-bit Parallel Subtractor the parallel binary subtractor is formed by combination of all full adders with subtrahend complement input.
This operation considers that the addition of minuend along with the 2’s complement of the subtrahend is equal to their subtraction.
Firstly the 1’s complement of B is obtained by the NOT gate and 1 can be added through the carry to find out the 2’s complement of B. This is further added to A to carry out the arithmetic subtraction.
The process continues till the last full adder FAn uses the carry bit Cn to add with its input An and 2’s complement of Bn to generate the last bit of the output along last carry bit Cout.<br>
08
4 bit parallel subtractor<br>
09
example 1010-1001
1010
1001 0110+(cin)1= 0111
1010
--------------
10001<br>
10
dvantages of parallel Adder/Subtractor –
The parallel adder/subtractor performs the addition operation faster as compared to serial adder/subtractor.
Time required for addition does not depend on the number of bits.
The output is in parallel form i.e all the bits are added/subtracted at the same time.
It is less costly.
Disadvantages of parallel Adder/Subtractor –
Each adder has to wait for the carry which is to be generated from the previous adder in chain.
The propagation delay( delay associated with the travelling of carry bit) is found to increase with the increase in the number of bits to be added.<br>
11
Parallel Adder / Subtractor<br>
12
When M= 1, the circuit is a subtractor and when M=0, the circuit becomes adder. The Ex-OR gate consists of two inputs to which one is connected to the B and other to input M. When M = 0, B Ex-OR of 0 produce B. Then full adders add the B with A with carry input zero and hence an addition operation is performed.
When M = 1, B Ex-OR of 0 produce B complement and also carry input is 1. Hence the complemented B inputs are added to A and 1 is added through the input carry, nothing but a 2’s complement operation. Therefore, the subtraction operation is performed.<br>
