ECE 424 Embedded Systems Design Lecture 11:
Description: ECE 424 Embedded Systems Design Lecture 11: Embedded Platform Boot Sequence Chapter 6 Ning Weng Introduction What is boot sequence? Why we care? 2 or 3 phases BIOSfireware: from processor reset vector OS boot loader: from storage devices
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slide1. ECE 424 Embedded Systems Design Lecture 11:
Embedded Platform Boot Sequence
Chapter 6
Ning Weng<br>
slide2. Introduction What is boot sequence?
Why we care?
2 or 3 phases
BIOS/fireware: from processor reset vector
OS boot loader: from storage devices
OS Ning Weng ECE 424 2<br>
slide3. Multi-core/threads Boot Basic terms
Thread, core, package and SOC,
Bootstrap processor (BSP), Aps
Wait-for-SIPI state: wait for startup inter processor interrupt Ning Weng ECE 424 3<br>
slide4. Image Storage Technologies Ning Weng ECE 424 4<br>
slide5. S1: Power Sequencing Ning Weng ECE 424 5<br>
slide6. S2: Reset Reset vector: the location of these initial processor instructions
Inel 16 bytes
Hardware and software reset
Operation modes
Real
Flat protected mode
Segmented protected mode Ning Weng ECE 424 6<br>
slide7. S3: Early Initialization CPU and memory controller initialization
CPU
IA Microcode update
Device Initialization
Memory Configuration
Post-memory setup
Shadowing
AP Initialization Ning Weng ECE 424 7<br>
slide8. S4: Advanced Initialization Platform related initialization, peripheral-specific
GPIO
Interrupt/Cache controller
Timers
PCIe bus
Image storage
… Ning Weng ECE 424 8<br>
slide9. S5: Boot Loader Identifying the image and handoff to the image
See next slides for overall boot flow Ning Weng ECE 424 9<br>
slide10. Ning Weng ECE 424 10<br>
slide11. PXE (Networking Booting) Ning Weng ECE 424 11<br>
slide12. Announcement Read chapter 7 for OS overview
Friday, 9/21 Exam 1
HW and Lab due Ning Weng ECE 424 12<br>
Embedded Platform Boot Sequence
Chapter 6
Ning Weng<br>
slide2. Introduction What is boot sequence?
Why we care?
2 or 3 phases
BIOS/fireware: from processor reset vector
OS boot loader: from storage devices
OS Ning Weng ECE 424 2<br>
slide3. Multi-core/threads Boot Basic terms
Thread, core, package and SOC,
Bootstrap processor (BSP), Aps
Wait-for-SIPI state: wait for startup inter processor interrupt Ning Weng ECE 424 3<br>
slide4. Image Storage Technologies Ning Weng ECE 424 4<br>
slide5. S1: Power Sequencing Ning Weng ECE 424 5<br>
slide6. S2: Reset Reset vector: the location of these initial processor instructions
Inel 16 bytes
Hardware and software reset
Operation modes
Real
Flat protected mode
Segmented protected mode Ning Weng ECE 424 6<br>
slide7. S3: Early Initialization CPU and memory controller initialization
CPU
IA Microcode update
Device Initialization
Memory Configuration
Post-memory setup
Shadowing
AP Initialization Ning Weng ECE 424 7<br>
slide8. S4: Advanced Initialization Platform related initialization, peripheral-specific
GPIO
Interrupt/Cache controller
Timers
PCIe bus
Image storage
… Ning Weng ECE 424 8<br>
slide9. S5: Boot Loader Identifying the image and handoff to the image
See next slides for overall boot flow Ning Weng ECE 424 9<br>
slide10. Ning Weng ECE 424 10<br>
slide11. PXE (Networking Booting) Ning Weng ECE 424 11<br>
slide12. Announcement Read chapter 7 for OS overview
Friday, 9/21 Exam 1
HW and Lab due Ning Weng ECE 424 12<br>