UNIT – 2 Basic Language Constructs of VHDL

Transcript:UNIT – 2 Basic Language Constructs of VHDL:
UNIT – 2 Basic Language Constructs of VHDL Advanced Digital System Design Contents Skeleton/syntax of VHDL program, Elements and program format, Objects, Data type and operators, Concurrent Signal Assignment, Combinational versus sequential circuits, Signal assignment statements, conditional signal assignment, Selected signal assignment, Conditional versus selected signal assignment statements Skeleton / Syntax of VHDL program A VHDL program is composed of a collection of Design Units A synthesizable VHDL program needs at least two design units: An Entity declaration An Architecture body Skeleton of typical VHDL program can be best explained by an example – even_detector as discussed earlier It describes the external interface, or “outline” of a circuit – which includes the name of circuit and the names and basic characteristics of its input and output ports In the example, entity declaration indicates that name of circuit is – even_detector and the circuit has a 3-bit input port, a, and a 1-bit output port, even Simplified syntax of an entity declaration is Port declaration contains following terms: Port_names, Mode Data_type Mode term indicates direction of signal, which can be in, out or inout The in and out keywords indicate that signal flows “into” and “out of” the circuit respectively The inout keyword indicates that signal flows in both directions and that corresponding port is bidirectional Mode term can also be buffer Port declaration above has 2 parts: a port – input signal having data type std_logic_vector(2 downto 0) which represents a 3-bit bus even port – output port having data type std_logic Note that any port with out mode cannot be used as an input signal It specifies the internal operation (behavioural model) or organization (structural or dataflow model) of a circuit In VHDL, we can develop multiple architecture bodies for the same entity declaration and later choose one body to bind with the entity for simulation/synthesis Simplified syntax of an architecture body is: First line shows the name of body and the corresponding entity It may contain an optional declarative section consisting of declarations of some objects, such as signals and constants which are used in architecture description The example has a declaration of internal signals: Main part of architecture body consists of concurrent statements that describe the operation or organization of circuit Design units are fundamental building blocks in VHDL program When a program is processed, it is broken into individual design units and each unit is analysed