Greenall 1 Current Status Current build of hybrids Version 3 distributed to 61 sites Cambridge DESY Freiburg LBL Liverpool and Santa Cruz Glasgow outstanding but pieces available once their jig sets made ID: 930030
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Slide1
Stave Hybrid Status
Ashley Greenall
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Slide2Current Status
Current build of hybrids (Version 3) distributed to 6(+1) sites:
Cambridge, DESY, Freiburg, LBL, Liverpool and Santa Cruz
Glasgow outstanding but pieces available once their jig sets made
Used as Mechanicals (gluing studies, wire-bonding) Leading to electrical test fixtures (DAQ evaluation) Will ultimately lead to module assemblyRecently received another 60 off circuits stuffed with passives59 passed visualOne single failure – solder splash on bond padQuality of soldering very goodElectrical performance of hybrids indicates no show stoppers BUT there are features Identified ‘break’ in Wshunt Disable line on hybrid (affects group of 9 asics in a single column)Affects operation of PPB slow control on stavelet – no other problems identifiedFix is trivial – requires addition of a single wire bond on a hybridStudies of shield-less hybrid show performance is not as expectedSee following slides
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Slide3Dtnoise
at 1fC L1A/COM
Regular pattern seen in Occ. on shield-less hybrid
Affects single (outer) column 0 of hybrid only
Not present on neighbouring column 12-3 BCOs widthNot seen on shielded type hybridTest done using L1A sent down COM line of hybridShield-less Hybrid3Dtnoise at 1fC using L1A lineL1A now sent down its own dedicated line on hybridNow see a different Occ. profile (compared to above)Again only seen on column 0Likewise not seen on shielded hybrid
Shield-less Hybrid
Shielded Hybrid
Shield-less Hybrid
Shielded Hybrid
In both instances this noise profile is not seen when conducting 3PT Gain scans.
Slide4Detailed view of the
Dtnoise
plots shows discrete
occupancy peaks at differing locations.
For the COM line, 4 discrete peaks per asic location:Strip pitch is ~75µm, noise peaks are 375µm wideCorresponds to ~5 channelsVia geometry is 380µm land Outlying occ. peaks are 20 channels apart, 1.5mmOutlying via separation is 1.43mm (c-to-c)Likewise for the L1A line, 3 peaks with similargeometry profile as aboveOutlying occ. peaks are 10 channels apart,
750µm
Outlying via separation is
750µm (c-to-c)
Points to noise injection from the
vias
No evidence of pickup from bus traces
20 channels
~5 channels
1.43mm
~10 channels
L1A line
COM line
750µm
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Shield-less Hybrid source of the noise
Slide5Hybrids are glued onto sensor asymmetrically
w.r.t
. Sensor strips
Simply done to ensure
asic
-to-sensor wire bonding geometry is correct
COM & L1A
vias
are sited directly above the column 0 strips, not the case for column 1 strips
Hence noise injection only seen on the one column of strips
Column 1 strips terminate here (at
asic
edge)
Column 0 strips terminate adjacent to opposite column readout
asics
Clearly passing under the
vias
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Shield-less Hybrid – why pickup on one column per hybrid
Slide6Shield-less Hybrid Performance – Why is it happening?
Ground + Top layer
Power and Ground layers of hybrids have voids around the signal trace
vias
Drill span is 1 to 4 i.e. plated-thru-holes through all four layers (done to keep the build simple & cost down)Vias are not blind – results in them ‘exposed’ on underside (up against sensor) with only glue layer separationWhereas for the shielded hybrid, bottom shield layer is not perforated – vias are blind up to layer 4Shield layer does it’s job – no evidence of pick up with this flavour of hybridVia patterning clearly seen through solder resist
Patterning is due to
asic
vacuum holes on FR4 carrier leaving imprint
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Shield + Top layer
Via patterning not so obvious
Solder resist removed to expose Cu of shield layer
Shield-less
Shielded
Fix would be to simply make signal
vias
(top 2 layers) blind for shield-less hybrid
Will result in a non-perforated ground (shield) layer
Slide7What next – near term
Planning for a new submission of the hybrid early September
Could go earlier BUT past experience of submitting during vacation time is not good
Hope to get layout files finalised by beginning of
AugustWill draw up a list of changes would like to take on board for this new submission and circulateFeedback from users would be useful about changes they would like to seeKnown changes are‘Fix’ to Wshunt Disable line Addressing minor issues regarding solder resist - in some cases makes wire-bonding difficult (Problem with BJ820 deep-access head)Likewise relocate a small number of bond padsComplete rethink of hybrid cut out tabs – after reflow cause the hybrid edges to riseConsider also extending the (sacrificial) tabs for module retainment within their frames i.e. glue these to frameWill re-visit Shield-less hybrid – address signal vias on top 2 layers to make blindRigid FR4 former (flex circuit glued to) will revert back to be plated (was not for version 3) – issue with warping
Plating should compensate for the
warping
Submission in September should result in hybrid availability late October
Which will then need to go for passive stuffing - expect their availability November
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Slide8What next – longer term
Preparing for ABC130 – hybrid issues
Proposal is for the topology of hybrid to change from 2 column
asic
readout to a single columnAssume that this is the defaultWhat level of redundancy will be taken on boardDuplicate CLK/COM buses etc.Sensor HV spec. Assume it is 500V + overhead – impacts on layout due to HV clearancesPropose a first attempt at hybrid layout with best guess of uncertaintiesUse realistic number of lines (CLK. COM. Data distribution)ABC130, HCC, Powering asic footprintsUseful exercise as it could be used to feedback optimal locating of asic pad locationsFurther material reductionsNumber of layers we can get away with and build detail (Kapton/Cu thicknesses etc.)Use of hatching Whilst maintaining yield/manufacturability
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