An RF platform to software developers amp system architects Operates over a much wider tuning range 70 MHz 6 GHz Works much better than the ADFMCOMMS2EBZ over the complete RF frequency RXTX RF ID: 644536
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Analog Devices, Inc. AD-FMCOMMS3-EBZ: An RF platform to software developers & system architectsOperates over a much wider tuning range, 70 MHz – 6 GHzWorks much better than the AD-FMCOMMS2-EBZ over the complete RF frequencyRX/TX RF differential-to-single-ended transformer is targeted for wider tuning range applicationsAn FMC: FPGA Mezzanine CardConnects to LPC: Low Pin Count expansion slot on Xilinx Zynq & Zedboard68 user-defined, single-ended signals or 34 user-defined differential pairs
Xilinx®
Zynq
™
SoC
:
Processing
System (
PS)
Dual-Core
ARM Cortex-A9
processor
Fixed architecture supports SW routines & operating systemsProgrammable Logic (PL)Equivalent fabric to an FPGAA flexible canvasIdeal for high-speed logic, arithmetic, & data flow subsystemsAXI InterconnectAdvanced Extensible Interface makes links between PL & PSConnects peripherals in PL, incl.: CoprocessorsCores for interacting with external interfaces (LEDs, switches, codecs)Additional memory elements
Implementation of a Full Duplex Transceiver using Xilinx
Zynq
SoC
and ADI RFCOMMS3 Board (1)
Benjamin Drozdenko, Rahman
Doost
, Kaushik Chowdhury, Miriam Leeser
HARDWARE SETUPSlide2
Benefits: Many blocks for DSP (e.g. FFT & IFFT) and communications (e.g. B/QPSK modulation) support automatic generation of HDL and C code; Easy generation of HDL and PL image using HDL Workflow AdvisorDisadvantages: As of R2015a, presently no way to model communications between PS & PL via AXI interconnect; not all blocks supported for HDL generation (e.g. correlation)PLPSRFCOMMS LPC
GigE
Receive Path
Transmit Path
PL
PS
RFCOMMS LPC
Receive Path
Transmit Path
User
Implementation of a Full Duplex Transceiver using Xilinx
Zynq
SoC
and ADI RFCOMMS3 Board (2)
Benjamin Drozdenko, Rahman
Doost
, Kaushik Chowdhury, Miriam Leeser
TOOLS OPTION 1: MathWorks products TOOLS OPTION 2: GNU Radio +
Vivado
Most computationally expensive signal processing blocks are run at the FPGA (e.g. Frame Preamble detection)
A balance has to be struck between
GNURadio
flexibility and System efficiency by dividing the design.
Changes in the HDL core and
LibIIO
(ADI)
driver needed.