Need for more ports PPI 8255 8255 8051 Interfacing Key board Interfacing LED Interfacing 7 Segment LED Interfacing IO Interfacing IO Devices connected through ports 8051 has 4 IO ports P0 to P3 ID: 320563
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Slide1
8051 I/O Interfacing
Need for more ports
PPI 8255
8255 – 8051 Interfacing
Key board Interfacing
LED Interfacing
7 Segment LED InterfacingSlide2
I/O Interfacing
I/O Devices connected through ports
8051 has 4 I/O ports P0 to P3.
In case 8051 needs external program and/or data memory
P0 and P2 are used for address bus & P0 is used for data bus.
Only 2 ports (P1,P3) remain i.e. only 2 I/O devices can be connected.
In case system application needs interrupt, serial I/O, i.e. alternate functions of P3
Only 1 port (P1) remain
i.e
only 1 I/O device can be interfaced.
Slide3
In case of 8031(Rom less version )
Program memory is external i.e. (P0 and P2) are not available for I/O interfacing.
If P3 in used for alternate functions then Only one port (P1) in available. We need more ports.Intel has designed programmable peripheral Interface (PPI) Intel 8255 for this purpose.Intel 8255 PPI has 24 I/O lines distributed to four ports.Port A – (8 Lines)Port B – (8 Lines)Port C – (Upper) – (4 Lines)
Port C- (Lower) – (4 Lines)Slide4
Each port can be programmed to be input or output.Individual port lines can’t be read or written to
- different from 8051 ports.
Ports have been put in two groups.Group A - Port A and Port C (Upper) (PA7 – PA0) (PC7 – PC4)Group B - Port B and Port C (Lower) (PB7 – PB0) (PC3 – PC0)Slide5
The 8255A block diagram.Slide6
D7- D0 – Used for data transfer between µp and 8255(Bidirectional)
RD (Input) - Read control Signal
WR (Input) - Write control Signal RESET (Input)- Resets the ports. Ports are configured an input ports on Reset.CS - Used to select the 8255 chip. Chip is selected based on the address decoding. A1, A0 - Are used to select the specified ports in 8255. - A1. A0 are lower 2 bits of as address lines.
Issued by µpSlide7
A1 A0
0 0 - Port A
0 1 - Port B 1 0 - Port C 1 1 - Control RegisterNote – There is no separate selection for Port C (Upper) or Port C (Lower) Port C is selected as a whole i.e. both upper and Lower ports are selected when A1, A0 = 10. Control Register is used to program the Ports as input or outputProgram the I/O mode.Slide8
The I/O ports can be programmed to work in any of the 3 modes Mode 0 - Basic Input –Output
Mode 1 - Strobed Input-Output
Mode 2 - Strobed Bidirectional Bus Mode 0 – Basic Input-Output majority of application fall under this mode. - Any port A , B, C(U) or C(L) can be input or outputSlide9
Mode 1- Strobed input-output - Provides means for transferring I/O data to or from a specified port in conjunction with strobes or hand shaking signals.
- Port C lines are used for hand shaking signals.
- Port A and Port B can be used as input or output. - Port A uses port C (Upper) lines for hand shaking – Group A - Port B uses port C (Lower) lines for hand shaking – Group BSlide10
Mode 2- Strobed Bidirectional Bus Port A can be used for input as well or output for transmitting as well as receiving the data in conjunction with hand shaking signals on Port C.
Hand shaking signals are provided to maintain proper bus flow direction
5 bits (PC7-PC3) of port C are used for hand shaking. Mode 2 is available for only Group A.Parallely Group B i.e port B can be used in mode 0 or 1.Configuring 8255- We have already mentioned that 8255 ports can be configured using control register (A1 A0 = 11).- The control word format for configuration of 8255 is shown Slide11Slide12
Example- We need to configure 8255 with Port A as input, Port B as output, Port C (L) as output, port C (upper) as input using mode=00Slide13
Note – Mode set flag i.e. D7=1 for all configuration. If this bit is one then only mode setting with be done by 8255.
Thus D7=1 , D5, D6=00-Mode 0, D4=1 (Port A=Input), D3=1[Port C(Upper)=Input], D2=0, (Mode=0) D1=0 (port B=output), D0=0 [ Port C(lower)=output]
So the Configuration byte = D7 D6 D5 D4 D3 D2 D1 D0 =98 HBy transferring 98H to control Register of 8255 will configure 8255 in the above manner.How -? We shall see after interfacing of 8255 with 8051.Note – The concept of 8255 configuration using control register has been used in 8051 in case of Timer, Serial I/O and interrupts.
1
0
0
1
1
0
0
0Slide14
8255 – 8051 Interfacing Let us review I/O mapped I/O and memory mapped I/O [Ref. Page 38-39 of Krishna Kant book.]
In I/O mapped I/O- The µp has separate instructions for memory and I/O read-write.
In addition µp will have separate control signals for I/O read-write and memory read-write. A variation of this may be that µp has same read-write control signal for I/O and memory but may have another signal to identify whether the read-write is for memory or for I/O. I/O and memory are treated separately Example – 8086 has IN and OUT as I/O read and write instructions. It has same RD (for read),WR (for write), signal for I/O and memory read- write. It has M/IO to identify memory or I/O read-write.Slide15
In memory mapped I/O I/O ports are treated as memory locations.
µp having memory mapped I/O.Will not have separate instructions for I/O and memory read-write.Will have only single read and write control signals for read and write.Will not have any signal to identify memory or I/O read-write. Example - 8051 has no separate instructions for memory and I/O read - write 8051 has only single read and write control signal Slide16
PSEN – external program memory read RD – External data memory read
WR - External data memory write
It has no signal to indentify whether read - write in for I/O or memory.Thus – I/O ports are treated as memory locations.Thus if we have to interface memory to 8051 , 8255 must be interfaced in external memoryExternal program memory can’t be written to .Thus 8255 must be interfaced in the external data memory.We need to select the address ‘XXXXH’ of memory The address on address lines to be decoded such that when ‘XXXXH’ is there, CS for 8255 is generated i.e 8255 needs to be selected.Slide17
RD (8051) connect to RD (8255)WR (8051) connect to WR (8255)
MOVX instructions to be used for data transfer from / to 8255
8255 has four portsWhen address lines A1 – A0 = 00 - Port A is selected = 01 - Port B is selected = 10 - Port C is selected = 11 - Control register is selectedThus last two bits starting address of 8255 address must be 00 Slide18
Assume that 8255 is interfaced at address FE10H Port A address = FE10H
Port B address = FE11H
Port C address = FE12H Control register address = FE13H MOV DPTR, # FEI3H MOV A, # 98H MOVX, @DPTR, A (will configure 8255) MOV DPTR, # FE10H MOVX A, @ DPTR (will bring the content of Port A to ACC.)Slide19
Address is sent to 8255 throughP0(Lower Address Byte) and P2(Higher Address Byte) Data is sent to/from 8255 through P0.
P0 acts both as Lower address lines as well as data lines in time multiplexed manner.
When Address is present, content of P0 must be latched , so that it can be used for data.Microprocessor sends a pulse on ALE when address is present.Slide20
High to Low transition of ALE may be used to latch the address on a latch.The latch can be connected to memory to give lower address byte.
P2 is directly connected to higher address lines of memory.Slide21
Two latch chips (octal latch) are popular
- 74LS373 - 8282 (by Intel)Both have 8 input lines & 8 output lines 74LS373 8282Input 1D to 8D DI0 to DI7Output 1Q to 8Q DO0 to DO7Tracking when Enable=1 when STB=1Latching when Enable=0 when STB=0Presenting when Enable OC=0 when OE=0
on outputSlide22
IF 74LS373 is used to latch the lower address byte
P0 – connected to input (1D to 8D) output (1Q to 8Q) connected to memory chip
- Enable is connected to ALE. - Thus when ALE is high, input is tracked. Input is latched on high to low transition of ALE. - OC is connected to ground. Thus latched data is available at output immediately.Slide23
7 4 L S 3 7 3
OC 1 20 VCC
1Q 2 19 8Q
1D 3 18 8D
2D 4 17 7D
2Q 5 16 7Q
3Q 6 15 6Q
3D 7 14 6D
4D 8 13 5D
4Q 9 12 5Q
GND 10 11 ENABLESlide24
Input - 1D to 8DOutput - 1Q to 8Q
When Enable = 1 Input is Tracked.
= 0 Input is Latched.When Output Control (OC) = 0 – latched output is present on output Slide25
Similarly for 8282STB is connected to ALE
OE is grounded.
VCC (+ 5V)
1 20
2 19
3 18
4 17
5 8282 16
6 or 15
7 8283 14
8 13
9 12
10 11
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
OE
GND
DO
0
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
STB
The 8282/8283 pin diagramSlide26
Input – DI0 to DI7Output – DO0 to DO7When STB = 1, Input is tracked
= 0, Input is latched
When Output Enable (OE) = 0, latched input is present on output.Slide27
P2
8051
ALE P0
74LS373
Or
8282
Address Decoder
CS
8255
RD
WR
A0
A1
A0 – A7
A2 – A7
A8 – A15
AD0 – AD7
D0 – D7Slide28
To generate CS for 8255 from given address. Assume address = FE10
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F E 1 0A1 , A0 are directly connected to 8255 and used for selection of I/O ports A,B,C and Control Regester. For selection of 8255 through CS, the address bits A2 to A15 may be decoded using simple gates.
1
1
1
1
1
1
1
0
0
0
01
000
0Slide29
A15
A14
A13
A10
A11
A12
A8
A9
A6
A7
A5
A2
CS of 8255
A4
A3
Many Variations of circuits are possible Slide30
If we select 8255 address as 0030H then decoding may be-
A5 A4
0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
A7
A6
A5
A4
A3
A2
CSSlide31
But it will generate Cs for 8255 for all address where A7 to A2 = 00 11 00i.e. 0030H, 0130H …………….FF30H
All these address will be valid for 8255 selection and are called address aliases – (aliases is used in general for other names identifying a person)
Problem - 1If selected address for 8255 = 8000H i.e. 1000 0000 0000 0000What will be decoding strategy ? Slide32
Problem -2 If 8255 address = 1110H Then what will be decoding
Decoder 74LS138 may also be used.Slide33
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
A15
A12
A1 A0
CS of
8255
OR
Decoding of 8255 Address E000H to generate chip select
A15
A13
A11
A12
A14
A10
A 9
A 8Slide34
Reading and writing to 8255 portsLet us assume that 8255 has been interfaced at address E000H the port addresses will be
Port A - E000H
Port B - E001H Port C - E002H Control register - E003HConsider that the application demands the following ports configuration Port A - Output Port B - Input Port C - OutputMode = 0 What will be control word of 8255 ?Slide35
The 8255 control word will be-1000 0010 =82H We may configure 8255 by writing 82H to control register in two ways:-
(A)
MOV DPTR, # E003HMOV A, # 82HMOVX @DPTR,ANote - E003 is location in external data 8255.Other way of writing (A) will be(B)PRA EQU E000HPRB EQU E001HPRC EQU E002HPRCR EQU E003H ORG 00H SJMP 030H ORG 030HSlide36
MOV DPTR, # PRCR MOV A, # 82H
MOVX @DPTR, A
To read data from Port B MOV DPTR, # PRB MOVX A,@DPTRTo write data to Port A MOV DPTR,# PRA MOV A,# Data MOVX @DPTR, ASlide37
Note :- 8255 ports ie . A,B,C have no addressable bits.
That to find status of individual bits –
Read port contextUse logical operations ANL ORL etc Or - Use shift/rotate RRC A , RRLC A etcIn keil bit (24 MHz, 8051) 8255 has been interfaced at addres E000HIn program (B) way of writing is normally used.Now let us take some I/O interfaceWe shall first take up Keyboard interfacing followed by LED interfacing and
7 segment LED interfacing
Slide38
Keyboard interfacing Basic keyboard operation is shown in figure
IN
High
OUT
(High when the key is pressed)
Basic keyboard operation-single key.Slide39
Basic keyboard operation- two keys.
OUT 1
OUT 2
INSlide40
OUT 3
OUT 2
OUT 1
OUT 4
IN
Basic keyboard operation – four keys.
Above Configuration can’t be adopted for more no. of keys
A 64 key keyboard will require EIGHT bit ports
We may represent the above as.Slide41
C
OUT1
OUT2
IN1
IN2
(1)
(2)
(3)
(4)
2x2 keyboard operation Slide42
Contains two rows – IN1 and IN2 and two columns OUT1 and OUT2 Activate Row1 i.e
IN1 check OUT1 (If 1 then key No. 1)
Else cheek OUT2 (If 1 then key No. 2)Activate Row2 i.e IN2 check OUT2 (If 1 then key No. 3)Else check OUT2 (If 1 then key No. 4)8 x 8 key board can be arranged in 8 rows and 8 columns.Only two ports are required to interface with µp.Slide43
8x8 keyboard interfacing with microprocessor Slide44
The codes of keys of key board may be stored row wise is 8255.
When a Key is pressed.
row no. and column no.
i.e. position of key is identified
key code is taken from table and used in the program.
Codes for keys
in the first row
Codes for
Keys
in the second row
Codes for keys
in
the eighth row
XX1
XX2
XX8
Code table for 8 x 8 keyboardSlide45
Start
I 1
Enable the
Ith
row
Set the address of the code for the first key on this row
Check for key depression
Key
Depressed
?
Determine the column number and the code of the key
I I+1
I>8
?
Yes
No
Yes
No
Keyboard- microprocessor interface software flowchartSlide46
Key Debouncing
When a key is depressed and released contact is not broken permanently.
Key makes and breaks the contact several time for few milliseconds before the contact is broken permanently. Thus a key depression detected by µp may be false i.e it may be due to bouncing of key. Thus key debouncing i.e. as certaining that key depression in true is important. Debouncing by HW and SW both in possible.
Software
debouncing
after key depression detected.
µp executes a delay routine for few milliseconds.
µp then again checks for key depression.
If key is depression is detected then real depression else false depression.
Slide47
Let us interface 4x4 keyboard with 8051Both rows and columns can be connected to 8 lines of one port.Rows can be activated by using SET B bit instruction.
Key Depression can be checked by using JB or JNB instructions.
Hex key pad interface in Lab. - 16 keys (0 to F) arranged in - 4 x 4 key boardRows connected to – PB0 to PB3Columns connected to – PA0 to PA3You have to determine the key depressionStore the code of the key in 8255.Slide48
Fig-33Slide49
LED Interface
LED
i.e Light Emitting Diode
emits light energy when conducts
Anode is held at higher voltage than
cathod
+5 V
LED operation.Slide50
LED interface with microprocessor
Common cathode Anode connected to Port Lines
All cathodes connected together to grounds
Port
Bit 7
Bit 0
Microprocessor interface to LED (common cathode)
[ Port bit = 1
LED Conducts
i.e
glows ]Slide51
Common Anode Anodes of all LED’s connected
together to 5V Cathodes of LED’s connected to port lines
Bit 7
Bit 0
+5 V
Microprocessor interface to LED (common anode).
[ Port bit = 0
LED Conducts
i.e
glows ]Slide52
In common cathode- by making individual port bits as “1” we may glow the LED. SETB P2.7
i.e
LED connected to P2.7 will glowMOV P2,#0FFH – All LED’s connected to port Port P2 will glowIn common Anode making a particular port bit ‘0’ will glow the LED connected to the port line.CLR P2.7- LED connected to P2.7 will glowMOV P2, # 00H- Will glow all the LED’s connected to port P2.Slide53
The structure has eight segments a,b,c,d,e,f,g and h. Very use full in displaying numeric and alphanumeric data.
Example :- For displaying A, all segments except d and h should glow.
a
b
c
d
e
f
g
h
Seven segment LED’s –
The LED’s can be arranged in the fashion shown
in Slide54
Character formation in seven segment LEDs
a
b
c
e
f
g
a
c
d
e
f
gSlide55
For displaying 6, all segments except b and h should glow.h is used for displaying decimal point.
Note – Previously there were only seven segments. Eighth segment h has been added later. But name seven segment has remained stock.
The On/Off in formation of segments can be arranged in one byte. Called control byte for 7 segment LEDThe bits (port lines) can be connected to segments as common cathode or common anode fashion. Common Cathode - Anodes connected to bits, cathodes connected to ground.Common Anode – Anodes connected to +5V, cathodes connected to bit. Slide56
Representing segment code in byte
- two ways
7 6 5 4 3 2 1 0
a b c d e f g h
7 6 5 4 3 2 1 0
h g f e d c b a
0-Glow the segment for common Anode configuration
1-Do not glowSlide57
Common Cathode -
bit =1, segment glows
bit = 0 – doesn’t glowCommon Anode - bit = 0 – segment glows bit = 1 – segment doesn't glowMicroprocessor can be interfaced to seven segment LED in parallel or serial way.Slide58
Parallel interface
+5 V
Anode
a
b
h
…
Resisters
Out port
7
6
0
Microprocessor interface to seven-segment LED (parallel interface).Slide59
in common Anode fashion Cathode of segments – connected to port bits.
MOV
Px, #00H – will glow all the segments CLR Px .3 – will glow segment No. 3 i.e segment ‘e’.Simple Hardware and software interfaceFor one 7 segment LED i.e display of 1 character one port is dedicated.Thus for displaying 20 characters, 20 ports will be required. Generation of ports will require extra hardware.Parallel interface is very fast but we don’t require very fast changing display due to limitation of our eyes.
Serial Interface-
Over
comes the limitation of parallel interface in case of large no. of 7 segment displays.
Slide60
Anode
a
b
h
…
Resisters
+5V
MSB
Shift register
LSB
Clock
Microprocessor interface to seven-segment LED(serial interface)
a
b
c
d
e
f
g
h
Code bitsSlide61
Contains – shift register connected to 7 segment LED.Two input lines- one for code bits and other for clock.
The operation sequence is shown in
Start
Load LSB from
display code
Load clock
Load next bit
Load clock
Seventh
bit loaded
?
Stop
No
YesSlide62
1
0
0
0
1
0
0
0
After 8 clock period the character will appear in 7 segment.
Example:- Display code for A
7 6 5 4 3 2 1 0
h g f e d c b a
for common anode configuration .
a
b
c
e
f
gSlide63
As bits move in shift register different segments glow and at the end of 8 clock periods ‘A’ appears. Connecting more segments doesn’t require any extra port or line. Using just clock and code bit line we may connect many segments in serial fashion. MSB of a segment is connected to input code bit line of shift register of next segment.Slide64Slide65
The characters will appear almost instantenously.
Large No. of 7 segment displays can be connected
74164 shift register is normally used. Any two port lines-one for clock and other for code bits may be used for displaying.Control byte may also be arranged as a b c d e f g hIn this case we shall Input MSBInput ClockSlide66
And continue doing it After 32 clocks, the 4 characters will appear in 4 -7 segment LED’sCoder bits of characters to be displayed may be stored in consecutive 8255 locations.
D0 D1 D2 D3
Code bits are sent in the order of D0 to D3.A segment counter is initialized to 32.After every clock – decremented When counter =0, - stop i.e. operation is completed 7 segment display experiment is part of microcontroller lab.