1 Digital Circuit Implementation Issues - PowerPoint Presentation

1. 1 Digital Circuit Implementation Issues PLAs, PALs, ROM’s, FPGA’s·      Packaging Issues·      Look Up Table method·      Multiplexer Method·      RAM & ROM method·      Xilinx and Actel Examples of FPGA’s·      I/O for FPGA’s·      Comparison of Various FPGAs  Lecture 12

2. 2Defining system requirementsMaking architectural decisionsDecisions on Hierarchy, Regularity, LocalityComprehensive design of units Planning for implementation Planning for verification Estimating System PerformanceImplementation Technology Decision Measuring system performanceImplementationBack to Design Cycle

3. 3PLD TypesNames associated with this field :PLD… PAL, PLA, FPLA SPLD, CPLDGA, MPGA, ASIC, Full Custom , Semi Custom, ROM, PROM, EPROM, EEPROM, FPGA, LCA, VLSI, ULSI, GSI, MCM, SOC, NoCFPOA (Field Programmable Object Array) eFPGA (embedded), FPGA, SOC FPGA, Stacked FPGA,MPSoc (multi processor FPGA,Ideal associated characteristics Field ProgrammabilityAvailability of CAD toolsCAD tool friendlinessPerformancePrototyping Costs, Production Time, Yield

4. 4Dsign AutomationSpecification HDL description Verify Design Target Technology Map design to PLD Download to PLDAutomatedAutomatic transformation of HDL code into a gate level netlist is called “SYNTHESIS”Every vender has its own tools for synthesis, however they all use the flow shown below

5. 5PLD Differences...Any Sum of Product (SOP)can be represented by AND-OR.ROM,PAL,PLA are different optimized implementation Of Given Circuit using the AND-OR planes.ROM: AND Fixed, OR ProgrammablePAL: AND Programmable, OR fixedPLA: AND Programmable, OR ProgrammableFPGA: Programmable Logic Blocks, Programmable Interconnect

6. 6PLDLogic Gates and ProgrammableswitchesInputs(logic variables)Outputs(logic functions)Programmable Logic Device as a black box

7. 7Input buffersAnd invertersANDPlaneORPlanex1 x2 xn-1 xnx1 x1 xn xnP1PkGeneral Structure of PLD – Programmable Logic DeviceAny combinational logic can be implemented with Sum of Productwhich is AND-OR implementation.PLDf1fm

8. 8ANDORDEVICEFixedFixedNot ProgrammableFixedProgrammablePROMProgrammableFixedPALProgrammableProgrammablePLAFunctionality Table

9. 9x1x2x3P1P2P3P4f1f2 Programmable Fuses ConnectionsOR planeSUMAND planePLA: Gate Level

10. 10OR planeP1AND planex1x2x3P2P3P4f1f2PLA: Customary Schematic

11. 11PLA....Advantages of PLA Efficient in terms of area needed for implementation on an IC chip Often included as part of larger chips such as microprocessors Programmable AND and OR gates

12. 12 OR plane (Fixed)P1 AND plane (Programmable)x1x2x3P2P3P4f1f2

13. 13PALPAL - Programmable Array Logic PLA have higher programmability than PAL, however they have lower speed than PAL Solution  PAL for higher speed. Programmable AND, Fixed OR PAL - Simpler to manufacture, cheaper than PLA and have better performance

14. 14 Flip-flops store the value produced by the OR gate output at a particular point and can hold it indefinitely. Flip-flop output is controlled by the clock signal. On 0-1 transition of clock, flip-flop stores the value at its D input and latches the value at Q output. 2-to-1 multiplexer selects an output from the OR gate output or the flip-flop output. Tri-state buffers are placed between multiplexer and the PAL output. Multiplexer’s output is fed back to the AND plane in PAL, which allows the multiplexer signal to be used internally in the PAL. This facilitates the implementation of circuits that have multiple stages (levels or logic gates).PAL- Extra circuitry....

15. 15D QSelectEnablef1ClockTo AND planeFlip-flopFor additional flexibility, extra circuitry is added at the output of each OR gate. This is also referred to macrocell.PAL- Extra circuitry: Macrocell

16. 16Example: FSM ImplementationS2 = P’ Q y1, R2 = y2, S1 = P’ Q’ , R1 = Q + P Z= y2 y1’ P Q’ , P & Q – are inputsy2 & y1 are the statesZ is the output

17. 17Programming of PLAs and PALsUser circuits are implemented in the programmable devices by configuring or programming these devices. Due to the large number of programmable switches in commercial chips; it is not feasible to specify manually the desired programming state for each switch. CAD systems are used to solve this problem.Computer system that runs the CAD tools is connected to a programming unit.After design of a circuit has been completed, CAD tool generates a file (programming file or fuse map) that specifies the state of each switch in PLD. PLD is then placed into the programming unit and the programming file is transferred from the computer system to the unit. Programming unit then programs each switch individually.

18. 18Programming of PLAs and PALs....PAL (or PLA) as part of a logic circuit resides with other chips on a Printed Circuit Board (PCB). PLD has to be removed from PCB for programming purposes. By placing a socket on PCB makes the removal possible. Plastic leaded chip carrier (PLCC) is the most commonly used package.Instead of using a programming unit, it would be easier if a chip could be programmed on the PCB itself. This type of programming is called in-system programming (ISP).So all you need: Personal computer, PLD CAD tool, The programming device and its software and the kind of PLD that the device accepts.Tutorial for PAL can be found athttp://courses.cs.washington.edu/courses/cse370/06au/tutorials/Tutorial_PAL.htm

19. 19Simple PLDs,Single AND_OR planeIt is configured by programming the AND and OR plane, or may be the Flip Flop inclusion and feedback selection,Usually has less than 32 I/OThey are available in DIP (Dual in line package), PLCC (Plastic Lead Chip Carrier up to 100 pins. Usually less than 100 equivalent gates.Complex PLDsMultiple AND-OR planesExtend the concept of the simple PLDs further by incorporating architectures that contain several multiple logic block PAL models. Most CPLD use programmable interconnect. Can accommodate from 1000 to 10,000 equivalent gates.Are available in PLCC and QFP (Quad Flap Pack) up to 200 pinsSPLD & CPLD...

20. Size of the Device related to:cost;speed;power.   Example:Implement the following functions on a PLAYou should choose:3 variable input5 product terms -> 5 AND gates4 outputs -> 4 OR gates

21. ProductInputOutputABCF0F1F2F311-1-1--01---11-01----00-11-1---1-1 For AND gate programmingFor OR gate programmingPersonality Matrix

22. After programming(* unused inputs of AND gates are connected to “1”; ** unused inputs of OR gates are connected to “0”)ProductInputOutputABCF0F1F2F3AB11-1-1-B’C-01---1AC’1-01---B’C’-00-11-A1---1-1 For AND gate programmingFor OR gate programmingPersonality Matrix

23. 23Chips containing PLDs are limited to modest sizes, typically supporting number of input and output more than 32. To accommodate circuits that require more input and outputs, either multiple PLAs or PALs can be used or a more sophisticated type of chip, called a complex programmable logic device (CLPD).CLPD is made up of multiple circuit blocks on a single chip, with internal wiring to connect the circuit blocks. The structure of CLPD is shown on the next slide. It includes four PAL-like blocks connected by interconnection wires. Each block in turn is connected to a sub-circuit I/O block, which is attached to a number of input and output pins.Complex Programmable Logic Devices: CLPD

24. 24Complex Programmable Logic Devices: CLPDPAL-like blockPAL-like blockPAL-like blockPAL-like blockInterconnection WiresI/OblockI/OblockI/OblockI/Oblock

25. 25D QD QPAL-like BlockPAL-like Block

26. 26CLPD uses quad flat pack (QFP) type of package. QFP package has pins on all four sides and the pins extend outward from the package with a downward-curving shape. Moreover, QFP pins are much thinner and hence, they support a larger number of pins when compared to the PLCC packing.Most CPLDs contain the same type of switch as in PLDs. Here, a separate programming unit is not used due to two main reasons. Firstly, CLPDs contain 200 + pins on the package, and these pins are often fragile and easily bent. Secondly, a socket would be required to hold the chip. Sockets are usually quite expensive and hence, add to the overall cost incurred.Programming of CLPDs

27. 27Programming of CLPDs....CLPD usually support the ISP technique. A small connector is included on the PCB and is connected to a computer system. CLPD is programmed by transferring the programming information from the CAD tool to into the CLPD. The circuitry on the CLPD that allows this type of programming is called JTAG, Joint Test Action Group port, and is standardized by the IEEE. JTAG is a non-volatile type of programming i.e programmed state is retained permanently (for example, in case of power failure, CLPD retains the program).

28. 28PLDs & FPGAsThe distinction between the two is blurredAlthough PLDs started as small devices, today’s PLDs are anything but simple.FPGAs fill the gap between PLDs and complex ASICsIn both cases, you can program the devices yourself, using design entry and simulation.All FPGAs have regular array of basic cells that are configured by the programmer using special software that program the chips by programming the interconnection.Each vendor has tool supplier that provides custom tools for their products.The programming methodology is usually non permanent, allowing re-programmability

29. 29FPGAs & MPGAsAdvantage:FPGAs have lower prototyping costsFPGAs have shorter production timesDisadvantage:FPGAs Have lower speed of operation in comparison to MPGAsSay by a factor 3 to 5FPGAs have a lower logic density in comparison to MPGAsSay by a factor of 8 to 12

30. 30FPGAs Consists of uncommitted logic arrays and user programmable interconnection.The interconnect programming is done through programmable switchesThe Logic circuits are implemented by partitioning the logic into blocks and then interconnecting the blocks with the programmable switchesThe architecture of an FPGA varies from device to device , vendor to vendor it can be based on CPLDs, EPROMS, EEPROMS, LUT, Buses, PALSThe interconnect is also varied from EPROM, static RAM, antifuse, EEprom

31. 31FPGAs ClassificationsImplementation ArchitectureLogic Implementation Interconnect TechnologySymmetrical ArrayRow based ArrayHierarchial PLDSea of GatesLook Up tableMultiplexer basedPLD BlockNAND GatesStatic RamAntifuseE/EPROMFPGA types

32. 32FPGAConsists of an array of uncommitted elements that can be interconnected in a general way. Likea PAL the interconnection between the elements are user programmable.The interconnect compromises segments of wires, where segments may be of various lengths. Present in the interconnect are programmable switches that serve to connect the logic blocks tothe wire segments or one wire segment to another. Logic circuits are implemented in the FPGA by partitioning the logic into logic blocks and then interconnecting the blocks as required via switches. To facilitate the implementation of a wide variety of circuits, it is important that an FPGA be as versatile as possible. There are many ways to design an FPGA, involving trade offs in the complexity and flexibility of both the logic blocks and the interconnection resources.

33. 33Logic Block and Interconnection:The architecture of logic blocks vary from simple combinational logic to complex EPROMs, LUT, Buses etc.. The routing architecture can also be variable including pass-transistors controlled by static RAM cells, anti fuses, EPROM transistors. Each company provides a variety of architecture of the logic blocks and routing architecture.FPGA....

34. 34Interconnect ResourcesLogic BlockI/O CellCONCEPTUAL FPGA

35. 35Row-basedInterconnectLogic BlockPLD BlockInterconnectoverlayed on LogicBlocksLogic BlockInterconnectSea-of-GatesHierarchical PLDInterconnectSymmetrical ArrayClasses of common commercial FPGAVarious Block Architecture & Routing Architecture

36. 36 Altera 40nm FPGA’ahttp://www.altera.com/literature/br/br-stratix-iv-hardcopy-iv.pdf Table 2. HardCopy IV E Devices OverviewDevice (1)ASICGates(2)MemoryBits(3)I/O PinsPLLsFPGAPrototypeHC4E2YZ3.9M8.1296 - 4804EP4SE110HC4E3YZ9.2M10.7296 - 4804EP4SE230HC4E4YZ7.6M12.1 - 13.3392 - 8644/8/12EP4SE290HC4E5YZ9.5M16.8480 - 8644/8/12EP4SE360HC4E6YZ11.5M16.8736 - 8808/12EP4SE530HC4E7YZ13.3M16.8736 - 8808/12EP4SE680Notes:Y = I/O count, Z = package type (see the product catalog for more information) ASIC gates calculated as 12 gates per logic element (LE), 5,000 gates per 18 x 18 multiplier(SRAMs, PLLs, test circuitry, I/O registers not included in gate count) Not including MLABs

37. 37Design EntryLogic OptimizationTechnology MappingPlacementRoutingProgramming UnitConfigured FPGADesign FlowProcess Diagram

38. 38Design Input…toxnf.XNFnetlistNetlist withoutdelaysxmakeLogic partitioninto CLBs.LCAnetlistppr/aprPlacing and routing.XNFnetlistPost layoutsimulationBack-annotated netlistwith delaysCreate programmingfilemakebits10011000…..BITfile4Start23567891Pre-layoutSimulatuionNetlistwith unitdelaysTo FPGA or PROMXilinx CellLibraryXilinx SoftwareXILINXFPGAProgrammingMethod

39. 39Implementation Process (overlook)A designer implementing a circuit on an FPGA must have access to CAD tools for that type of FPGA. The following steps summarize the process Logic Entry: Either simulate capture or entering VHDL description or specifying Boolean expansions. Translate to Boolean & optimizeTransform into a circuit of FPGA logic blocks through a technology mapping program (minimizing # of blocks). Decides what to place in each block in FPGA array (minimizing total length of interconnect) Assigns the FPGA’s wire segments and chooses programmable switches to establish required interconnection.

40. 40 The output of the CAD system is fed to the programming unit that configures the final FPGA chip.Depending upon correct VHDL or design entry, the entire process ofimplementing a circuit in an FPGA can take from a few minutes to about and hour.Implementation Process (overlook)....

41. 41Shannon's Expansion TheoramAny logic function can expanded in form of a Boolean variable:F= A.F + A.FFor example assume F= A.B + A.B.C + A . B. CThen in the expansionF = A [A.B + A.B.C + A. B. C]+ A [ A.B + A.B.C + A. B. C ] = A. [B.C ] + A [ B + C ] Then this can be implemented with a MUX FAF1F2F1 F2

42. 42F1 = B . C F2 = B + C These functions can be broken down further into:F1 = B ( B . C ) + B ( B . C ) = B . C + B . 0F10CBF2 = B ( B + C ) + B ( B + C ) = B . 1 + B . CF2C1BF2C1BF10CBFAOverall FunctionShannon's Expansion Theoram....01MUXControl

43. 43Shannon's Expansion TheoramFunctions can also be expanded into canonical form. Then F is expanded as F= A.B + A.B.C + A . B. CF = A . B ( C + C ) + A . B . C + A . B . C = A . B . C + A . B . C + A . B . C + A . B . C = A . B . C + A ( B . C + B . C + B . C ) = A . F1 +A. F2 In turn this can be implemented in MUX:FAF1F2

44. 44Therefore 2-1 multiplexer is a general block that can represent any gate:AND GateF = A . BF = A . ( A . B ) + A ( A . B ) = A . B + A . 0F0BAF = A ( A + B ) + A’ ( A + B ) = A + AB + A’. B = A . 1 + A’ . BF1ABF = A . B + A . BCBABOR GateEx-ORShannon's Expansion Theoram....

45. 4510 ‘1’‘1’Functions that can be implemented using just 2:1 MUX (No inverter at the input).If there are no 2 input rails available, XOR, NAND & NOR cannot be implementeddirectly. There is a need for more MUXs to be used as inverters.

46. 46ACT1 module has three 2:1 Muxs with AND-OR logic at the select of final MUX and implements all 2 input functions, most 3 input and many 4 input functions. Software module generator for ACT1 takes care of all this. Apart from variety of combinational logic functions, the ACT1 module can implement sequential logic cells in a flexible and efficient manner. For example an ACT1 module can be used for a transparent Latch or two modules for a flip flop.ACTEL (Microsemi)FPGAhttp://www.actel.com/documents/MX_DS.pdf

47. 47I/O BlocksI/O BlocksLogicModule RowsI/O BlocksI/O BlocksChannel RoutingGeneral Architecture of Actel FPGAsSAA0A1B0B1SBS1YS0ACT-1 Logic Module

48. 48LMLMLMLMLMLMLMLMLMLMInput SegmentWiring SegmentAnti fuseClock TrackVerticalTrackOutput TrackThe basic Architecture of Actel FPGA is similar to that found in MPGAs, consisting of rowsof programming block with horizontal routing channels between the rows. Each routing switchin these FPGAs is implemented by the PLICE Anti fuse.Connections are all and orbut shown only in this sectionfor clarityAct 1 Programmable Interconnect Architecture

49. 49M1A0A1SAB0B1SBS0S1O1S3F2SF1M2F010101A0SAB0B1S3F2F1M2S0S1SBA1O1S3FM1D‘1’CD‘1’A‘0’BO1S3F2SF1M2F010101F = A.B + B.C +D = B [A.B + B.C + D] + B[A.B + B.C + D] = A.B + B.D + B.C + B.D = B.(A+D) + B (C+D)ACTEL Logic ModuleACTEL – Implementation using pass transistorsACTELAn example logic macro

50. 50M1D00D01B1OUTYD10D11A1B0A0S1S0ACTEL ACT C-ModuleM1D00D01B1D10D11A1CLRA0S1S0QSECLKYCLKD00D01B1D10D11A1B0A0S1S0QSEYCLRS-Module (ACT 2)S-Module (ACT 3)101 0ZZQDC2C1CLRCombinational Logic for Clear and ClockMaster LatchSlaveLatchSE (Sequential Element)DQCLKC2C1CLRCLRSE

51. 51ACT1 AND ACT3 LOGIC MODULES ACT1 module is simple logical block. It does not have built in function to generate a Flip Flop. Although it can generate a FF if required. ACT2 and ACT3 that has separate FF module is used for Sequential Circuits.Timing Models & Critical PathExact timing (delays) on any FPGA chip cannot be estimated until place and routing step has been performed. This is due to the delay of the interconnect. A critical path of SE in is shown on the next slide.

52. 52View frominside lookingoutView fromoutside lookinginModel with numerical valuesTaking S-moduleas one sequential cctActel ACT3 timing model

53. 53TABLE 5.2  ACT 3 timing parameters* [1]  Fanout Family Delay*1 2 3 4 8 ACT 3-3 (data book)t PD 2.93.23.43.74.8ACT3-2 (calculated)t PD /0.853.413.764.004.355.65ACT3-1 (calculated)t PD /0.753.874.274.534.936.40ACT3-Std (calculated)t PD /0.654.464.925.235.697.38   * V DD = 4.75 V, T J ( junction) = 70 °C. Logic module + routing delay. All propagation delays in nanoseconds.* The Actel '1' speed grade is 15 % faster than 'Std'; '2' is 25 % faster than 'Std'; '3' is 35 % faster than 'Std'.ACT timing parameters

54. 54ACT timing parameters....TABLE 5.3  ACT 3 Derating factors* [1]  Temperature T J ( junction) / °C V DD / V–55 –40 0 25 70 85 125 4.50.720.760.850.901.04 1.071.174.750.700.730.820.871.001.031.125.000.680.710.79 0.840.971.001.095.250.660.690.770.820.940.971.065.50.630.660.74 0.79 0.900.931.01Worst-case (Commercial): V DD = 4.75 V, T A (ambient) = +70 °C. Commercial: V DD = 5 V ± 5 %, T A (ambient) = 0 to +70 °C. Industrial: V DD = 5 V ± 10 %, T A (ambient) = –40 to +85 °C. Military V DD = 5 V ± 10 %, T C (case) = –55 to +125 °C.

55. 55A k input LUT can implement any Boolean function of k variables. The inputs are used as addresses that can retrieve the 2k by 1-bit memory that stores the truth table of the Boolean function. Since the size of the memory increases with the number of inputs, k, in order to optimize this mapping and reduce the size of the memory there are a variety of algorithms that map a Boolean network, from a given equation, into a circuit of k-input LUT. These algorithms minimize either the total number of LUTs or the number of levels of LUTs in the final circuit. Minimizing the total number of LUTs reduces the CLB requirements while minimizing the levels of LUTs improves the delay.Look Up Table (LUT)

56. 56A LUT in reality is a truth table implementation and as such any combinational circuit can be built with variables as address lines.A RAM ( A table) will contain the values of the gate or a desired function. Addressing the function is done by Muxes to select the output. Also the RAM and addressing can be created at implementation level by programming the RAM and the Muxes.So for any fixed number of variables the circuit is the same.All the functions with the same number of variables, thus created will have the same delay.For any fixed number of variables, various functions implemented with LUT, the area, Delay and Power is the same.The evaluation of the Delay, Area and Power is simple and more accurate.Re-programming is simple since only memory has to be changed.Example: A full CASE statement in VHDL can easily be translated to a LUT.Most current FPGA manufacturers use LUT in their FPGAsExample: Today's technology uses 6 input wide SRAM so you have to have 32 + 16 + 8+ 4+ 2+1 2 to 1 Muxes for reading the contents.Advantages of Look Up Table

57. 57f1= (abc + def) (g + h + i) (jk +lm)a b c d e f g h l j k l mxyza b c j k l mxyzg h id e f4 input LUT5 input LUTThis can be implemented by Four 5 input LUTLookUp Tables: LUT....[1]

58. 58Two input LUTBefore programming x1x2f1001010100111f1= x1 x2 + x1 x2 Function to be implementedLookUp Tables: LUT....Storage Cell contents in the LUTAfter programming 1 0 0 1

59. 59Storage Cell contents in the LUTAfter programming 1 0 0 10101f1f1= x2 x1+ x2 x1LookUp Tables: LUT....

60. 60Extra Circuitry in FPGA logic blockD QSelectClockFlip-flopLUTIn1In2In3ABCF00000010010001101000101011001111LUT....

61. 61Three - input LUTDDataread/writeQQ 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

62. 62Xilinx uses the configuration cell, ie a static ram shown to store a ‘1’ or ‘0’ to drive the gates of other transistors on the chip to on or off to make connections or to break the connections.The cell is constructed from two cross-coupled Inverters and uses standard CMOS process.This method has the advantage or immediate re-programmability. By changing the configuration cells new designs can be implemented almost immediately. New designs encoded in a bit patterns can be sent directly by any sort of mail if needed.The disadvantage of using SRAM technology is it is a volatile technology. If power is turned off then, the information is lost. Alternatively, configuration data can be loaded from a permanently programmed memory (PROM) so that every time the system is turned on, the information regarding cells are down loaded automatically.The SRAM based FPGAs have a larger area overhead (5Transistors/cell) than the fused or anti fused devices. Advantages are fast programmability and uses standard CMOS ProcessStatic RAMRAM cellQQ

63. 63RAM cellRoutingwireRAM cellRoutingwireRouting wireRAM cellRAM cellMUXTo logic cell inputStatic RAM....

64. 64An anti fuse is normally an open circuit until a programming current is forced though it (about5mA @ 18 Volts).The two prominent methods are Poly to Diffusion (Actel) and Metal to Metal (Via Link). In a Poly-diffusion anti fuse the high current density causes a large power dissipation in a smallarea. Once fused The contact is permanent.Anti fuse Polysiliconn+ DiffusionDielectric2 λAnti fuse PolysiliconAnti fusePolysiliconAnti fusen+ anti fuse diffusionContactThe actual anti fuse link is less than 10nm x 10nmAnti fuse (Actel)

65. 65This will melt a thin insulating dielectric between polysilicon and diffusion and form a thin(about 20nm in diameter) permanent, and resistive silicon link. The programming process alsodrives dopand atoms from the poly and diffusion electrodes. The fabrication process and Programming current controls the average resistance of blown anti fuses.Actel Device # of Anti fuses A1010 112,000A1225 250,000A1280 750,000 250 500 750 1000Anti fuse Resistance in Ω% Blown Anti fusesTo design and program an Actel FPGA, designers iterate between design entry and simulationwhen design is verified both by functional tests. Once a designer has completed place-and-route using Actel's Designer software and verified its timing, the program generates an AFM (Actel fuse map) programming file. The Chip is plugged into a socket on a special programming box that generates the programming voltage. Anti fuse (Actel)….Anti fuse (Actel)…. http://www.ee.ic.ac.uk/pcheung/teaching/ee3_DSD/3-FPGA%20Technology.pdf

66. 66Metal-Metal Anti fuse (Via Link)Same principle as previous slide but different process with 2 main advantagesDirect metal to metal eliminating connection between poly and metal or diffusion to metal thus reducing parasitic capacitance and interconnect space requirement.Lower resistance.Anti fuseRouting wiresRouting wiresM3M2Thin amorphous SiM3 4λM2 4λ 2λ 50 80 100Anti fuse Resistance Ω% Blown Anti fusesAnti fuse (Actel)….

67. 67Altera MAX 5K and Xilinx ELPDs both use UV-erasable “electrically programmable read-only ` memory” (EPROM) cells as their programming technology. The EPROM cell is almost as small as an anti fuse. GroundSDG2G1SDG2G1+Vgs>Vtn+Vpp+Vgs>VtnVdsNo channelG2G1UV lightEPROM and EEPROMEEPROM Is a special process that the transistor has double gate one for selection and a floating gate for programming./re-programming.Disadvantage is slow re-configuration time , high ON_Resistance due to the floating gate, high static power consumption. Advantages being non-volatile.

68. 68Altera MAX 5K and Xilinx ELPDs both use UV-erasable “electrically programmable read-only memory” (EPROM) cells as their programming technology. The EPROM cell is almost as small as an anti fuse.An EPROM looks like a normal transistor except it has a second floating gate.Applying a programming voltage Vpp (>12) to the drain of the n-channel, programs the cell. A high electric field causes electrons flowing towards the drain to move so fast they “jump” across the insulating gate oxide where they are trapped on the bottom of the floating gate.Electrons trapped on the floating gate raise the threshold voltage. Once programmed an n-channel EPROM remains off even with Vdd applied to the gate. An unprogrammed n-channel device will turn on as normal with a top-gate voltage Vdd.Exposure to an ultra-violet (UV) light will erase the EPROM cell. An absorbed light quantum gives an electron enough energy to jump for the floating gate. EPROM and EEPROM….

69. 69EPLD package can be bought in a windowed package for development, erase it and use it again. Programming EEPROM transistors is similar to programming an UV-erasable EPROM transistor, but the erase mechanism is different. In an EEPROM transistor and electric field is also used to remove electrons from the floating gate of a programmed transistor. This is faster than the UV-procedure and the chip doesn’t have to removed from the system. EPROM and EEPROM….

70. 70Programming TechnologyVolatileRe-Program.Chip AreaR(ohms)C(ff)Static RAMCellsyesIn circuitLarge1-2K10-20 ffPLICEAnti-fusenonoSmall anti-Fuse. LargeProg. Trans.300-5003-5ffVia LinkAnti-fusenonoSmall anti-Fuse. LargeProg. Trans.50-801.3ffEPROMnoOut ofCircuitSmall2-4K10-20ffEEPROMnoIn Circuit2x EPROM2-4K 10-20ffEPROM and EEPROM….Table 2.1 Characteristics of Programming Technologies

71. 71Can be static RAM cells, Anti fuse, EPROM transistor and EEPROM transistors.The programming elements are used to implement the programmable connections among the FPGA’s logic blocks, and a typical FPGA may contain some 5000,000 programming elements.The programming element should consume as little chip area as possible.The programming element should have a low “ON” resistance and very high “OFF” resistance.The programming element contributes low parasitic capacitance to the wiring.It should be possible to reliably fabricate a large number of programming elements on a singe chipRe-programmability is derived features for these elements.Programming Technology

72. 72FPGAsImplementation Architecture:Symmetrical ArrayRow basedHierarchical PLDSea of GatesLogic ImplementationLook Up TableMultiplexer basedPLD BlockNAND gatesTechnology of Interconnection Static RAM Anti fuse EPROM EEPROMFPGAs

73. Modern hardware development process is based on HDL designs and IP core. Standard cell ASIC design cost is in millions of dollars, effectively making the FPGA the best alternative.Example the XILINX Vertix 4 FF series has the following COREs:PowerPC® processors (with a new APU interface), tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers,dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks, 18 x 18, two’s complement, signed Multiplier with Optional pipeline stagesAnd Built-in Accumulator (48-bit) Adder/Subtracter

74. Embedded UnitsIn more complex FPGAs There are many specialized circuitry, particularly for DSP.These include a variety of Adders, Multipliers, Processors Memory Digital to Analog converters and so on. For example: Memory units of RAM 16 K to 10M RAM with different organizationsMultipliers 25 * 18 bits or 18 * 18 bits multipliers from Xilinx, and AlteraAdders A variety of adders example 48 bit adders from XilinxProcessors MicroBlaze, IBM Power PC, Pico Blaze, from Xilinx– ARM 9, Nios, MIPS from Altera

75. FPGA market is expected to reach USD 7.23 Billion by 2022A key influencing factor for the growth of FPGAs is their fast time-to-market (TTM). FPGAs offer fastest TTM, compared to their counterparts ASICs and ASSPs?ASIC: Application Specific Integrated Circuits.ASSP : An application specific standard product. ASSP is an integrated circuit that implements a specific function that is used in a wide market. ASICs combine a collection of functions and are designed by or for one customer. FPGA Growth

76. XilinxInc., Achronix Semiconductor Corp., Atmel Corporation, Altera Corporation, Lattice Semiconductor Corporation, Atmel Corporation, Tabula Inc., and Microsemi Corporation.FPGA Manufacturers and their market share (2016)

77. FPGA Applicationsthe global FPGA market is categorized as: Telecommunication, Military & Aerospace, Consumer Electronics, Industrial, Automotive, Medical, Computing, Others

78. FINAL WORDSThe FPGA Cores (IP modules):Prevents others from looking inside the core to see how they work. Many FPGAs have an array of IP (Pre made modules) can perform many complicated tasks. Example: IP modules that implement a soft CPU that can be used as a general computer. FPGA AdvantagesThe design can be written, tested and simulated on the computer. The Verified designs can be portable to other FPGA devices, for repeatable and rapid deployment Multiple people can work on the same HDL files and increase the speed of circuit development.FPGA can be rewritten as many times as needed. The flash memory, which stores the program to configure the FPGA on power up, will be the limiting factor, with a re-write limit of about 100,000.There are Many FPGA coming to the market every day What I gave you is a basic principal Always keep uptodate and choose the right FPGA that fits your requirementsExample: Current Xilinx product portfolio based on 28nm and 20nm planar and 16Fin FET+ technologies and keeps changingFINAL WORDS ON FPGAS

79. FeaturesArtix-7Kintex-7Virtex-7Spartan-6Virtex-6Logic Cells352,000480,0002,000,000150,000760,000BlockRAM19Mb34Mb68Mb4.8Mb38MbDSP Slices1,0401,9203,6001802,016DSP Performance (symmetric FIR)1,248GMACS2,845GMACS5,335GMACS140GMACS2,419GMACSTransceiver Count163296872Transceiver Speed6.6Gb/s12.5Gb/s28.05Gb/s3.2Gb/s11.18Gb/sTotal Transceiver Bandwidth (full duplex)211Gb/s800Gb/s2,784Gb/s50Gb/s536Gb/sMemory Interface (DDR3)1,066Mb/s1,866Mb/s1,866Mb/s800Mb/s1,066Mb/sPCI Express® InterfaceGen2x4Gen2x8Gen3x8Gen1x1Gen2x8Agile Mixed Signal (AMS)/XADCYesYesYes YesConfiguration AESYesYesYesYesYesI/O Pins6005001,2005761,200I/O Voltage1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V1.2V, 1.5V, 1.8V, 2.5V, 3.3V1.2V, 1.5V, 1.8V, 2.5VEasyPath Cost Reduction Solution-YesYes-YesFPGA Comparison Table

80. 80CompanyGeneral ArchitectureLogic BlockTypeProgramming TechnologyXilinxSymmetrical ArrayLook-up TableStatic RAMActelRow-basedMultiplexer-BasedAnti-fuseAlteraHierarchical-PLDPLD BlockEPROMPlesseySea-of-GatesNAND-gateStatic RAMPLUSHierarchical-PLDPLD BlockEPROMAMDHierarchical-PLDPLD BlockEEPROMQuickLogicSymmetrical ArrayMultiplexer-BasedAnti-fuseAlgotronixSea-of-gatesMultiplexers & Basic Gate Static RAMConcurrentSea-of-gatesMultiplexers & Basic Gate Static RAMCrosspointRow-basedTransistors Pairs &MultiplexersAnti-fuseFPGAs….[1]Table 2.2 Summary of Commercially Available FPGAs

81. 81TAB (Taped Automated Bonding)PQFP(Plastic Quad Flat Package)PLCC(Plastic Leaded Chip Carrier)DIP(Dual In-line Package)

82. 82Classic Package Hierarchy [Intel Corp.] BoardSilicon Die~ .040”~ .012“Package

83. 83Area Array PackagesCross Section of Flip-Chip Ball Grid Array(FC-BGA)

84. 84Which Package should we select?Industry trend is going for Area Array PackagesBond wires contribute parasitic inductanceAccording to some policies, industry is urged to use pb-Free productsThe number of needed pins growing upPackaging InnovationsSystem In Package (SiP) Wafer Level Package (WLP) Wafer Level Packaging (WLP)System in Package (SiP)

85. http://electronics.stackexchange.com/questions/128120/reason-of-multiple-gnd-and-vcc-on-an-ic (90nm Technology)

86. Current has to be distributed, it is impractical that any pad can take the total current. The resistance drop is prohibitingPower coming in from any one pin will probably have to snake it's away around a lot of stuff to get to every part of the device. Multiple power lines gives the device multiple avenues to pull power from, which keeps the voltage from dipping as much during high current events.Need for a clean supply voltage at certain areas.Analog devices require special attention and probably different voltage supply.Heat distribution, and removalReasons for having multiple supply lines.

87. http://electronics.stackexchange.com/questions/128120/reason-of-multiple-gnd-and-vcc-on-an-icThe figure represents all of the power and ground pins on a Virtex 4 FPGA in a BGA package with 1513 pins. The FPGA can draw up to 30 or 40 amps at 1.2 voltsEvery I/O pin is adjacent to at least one power or ground pin, minimizing the inductance and therefore the generated crosstalk.

88. 88Todays generation of FPGAs consist of various mixes of configurable embedded Ips (large blocks) such as: SRAM, transceivers, I/Os, logic blocks, Arithematic units such as adders and multipliers, microprocessors and routing. Most FPGAs contains programmable logic components called logic elements (LEs) and a hierarchy of reconfigurable interconnects You can configure LEs to perform complex combinational functions, or merely simple logic gates. Most FPGAs, include memory elements, which may be simple flipflops or complete blocks of memory.Today’s FPGAs structure

89. INTEL’s Falcon MesaIntel's® next generation of field programmable gate arrays (FPGAs) will use Intel's own 10-nanometer (10 nm) chip-manufacturing process technology - Known today by the codename “Falcon Mesa,” these FPGA products will target the acceleration and compute needs in data center, wireless 5G, Network Function Virtualization (NFV), automotive, industrial, and military/aerospace applications. 112 Gbps serial transceiver links to support the most demanding bandwidth requirements in next generation data center, enterprise, and networking environments. Latest peripheral device interconnect including PCI Express Gen4 x16 support with data rates up to 16 GT/s per lane for next generation data centers.Intel’s next-generation Embedded Multi-Die Interconnect Bridge (EMIB) packaging technology for continued leadership in hetergeneous 3D system-in-package (SiP) integration. The second generation will be optimized for higher levels of transceiver performance alongside a monolithic FPGA fabric.Next-generation high bandwidth memory (HBM) support, a DRAM memory architecture that delivers 10x the performance of discrete memory solutions in a smaller form factor with lower power consumption

90. 90Highest bandwidth, highest integration 28-nm FPGAs with ultimate flexibilityNew class of application-targeted devices with integrated 28-Gbps and backplane-capable 12.5-Gbps transceivers, integrated hard intellectual property (IP) blocks including Embedded HardCopy® Blocks, and user-friendly partial reconfiguration30% lower total power compared to Stratix® IV FPGAsLow-risk, low-cost path to HardCopy ASICs for higher volume productionAltera’s Stratix’advertisement

91. 9128-nm FPGAs providing industry’s lowest system cost and powerSix variants offer mix of logic, 3.125-Gbps or 5-Gbps transceivers, and single- or dual-core ARM Cortex-A9 hard processor systemDelivers up to 40 percent lower total power and up to 30 percent lower static power vs. the previous generationHigh level of integration with abundant hard IP blocksAltera’s Cyclone advertisement

92. Altera’s Cyclone II FPGA Starter Development Board (around $200.)92

93. As it matures, the cost of 20 nm technology may never cross over the cost of 28 nm technology.93

94. Xilinx future trends94benefit from the performance per watt advantages of FinFET technology.                                                                                                                                                                                                 Figure 1: Xilinx continues to expand its leadership in all three areas.Innovations at 16nm: UltraScale+ FamilyBuilding on the core UltraScale architecture at 20nm, Xilinx’s 16nm UltraScale+™ family of FPGAs, 3D ICs and MPSoCs, combine new UltraRAM and High-Bandwidth Memory (HBM), 3D-on-3D and multi-processing SoC (MPSoC) technologies, delivering a generation ahead of value. To enable the highest level of performance and integration, the UltraScale+ family also includes a new interconnect optimization technology, SmartConnect. These devices extend Xilinx’s UltraScale portfolio - now spanning 20nm and 16nm FPGA, SoC and 3D IC devices - and leverage a significant boost in performance/watt from TSMC’s 16FF+ FinFET 3D transistors. Optimized at the system level, the UltraScale+ family delivers far more systems integration and intelligence, and the highest level of security and safety than previous generations of technology.The newly extended Xilinx UltraScale+ FPGA portfolio is comprised of Xilinx’s market leading Kintex® UltraScale+ FPGA and Virtex® UltraScale+ FPGA and 3D IC families, while the Zynq® UltraScale+ family includes the industry’s first all programmable MPSoCs.Zynq UltraScale+ MPSoC – The 2nd Generation All Programmable SoCThe UltraScale+™ MPSoC Architecture, built on TSMC’s 16nm FinFET process technology, enables next generation Zynq UltraScale MPSoCs. This new architecture provides processor scalability from 32 to 64 bits with support for virtualization, the combination of soft and hard engines for real time control, and graphics/video processing, waveform and packet processing, next generation interconnect and memory, advanced power management, and technology enhancements that deliver multi-level security, safety and reliability. These new architectural elements are coupled with the Vivado® Design Suite and abstract design environments to greatly simplify programming and increase productivity. Figure2 : The Xilinx UltraScale MPSoC architecture delivers the right engines for the right tasks.Industry’s First 3D on 3D TechnologyThe high end of the UltraScale+ portfolio leverages the combined power of 3D transistors and 3rd generation of Xilinx 3D ICs. Just as FinFETs enable a non-linear improvement in performance/watt over planar transistors, 3D ICs enable a non-linear improvement in systems integration and bandwidth/watt over monolithic devices. Figure 3: Xilinx’s 3rd generation 3D ICs will come in homogeneous and heterogeneous configurations.Next Generation Design Suite & MethodologyBuilt from the ground up for Xilinx’s 28nm portfolio, the Vivado Design Suite has been co-optimized with the UltraScale architecture to deliver significant quality of results, routability, utilization, and productivity advantages. When combined with UltraFast™, a potent methodology that covers all aspects of board planning, design creation, design implementation and closure, programming and hardware debug, design teams will be able to accelerate their time to predictable success.Productivity for the front end design process is multiplied by more than 4X with high level synthesis and IP integration tools. Productivity in design implementation improves by more than 4X due to faster hierarchical planning and analytic place and route engines as well as support for fast incremental ECOs.The method of update allows customers to migrate their 20nm designs and benefit from the performance per watt advantages of FinFET technology.

95. 95Birds-eye view of circuit board with individually packaged chipsBirds-eye view of circuit board witha System-on-Chip (SoC) deviceBirds-eye view of circuit board with a System-in-Package (SiP) deviceBirds-eye view of circuit board with a System-in-Package (SiP) device2D vs. 2.5D vs. 3D ICs 101 By:Clive Maxfield 4/8/2012 12:08 PM EDT

96. 96A simple form of 3D IC/SiPConnecting dice using wires running down the sides 3D stackA simple “True 3D IC/SiP”A more complex “True 3D IC/SiP3D Structures2D vs. 2.5D vs. 3D ICs 101 By:Clive Maxfield 4/8/2012 12:08 PM EDT

97. 97Project Team work

98. 98Three - input LUTDDataread/writeQQ 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

99. Many views of the same Object99

100. FINAL WORD12/13/2019100 Thank you for being good students. I hope you have learned something in this class, that it will be useful in your future endeavor.Always go to the root of any problem that you are solving, whether engineering or social.Be a Good engineer, Never forget your Engineering ethics.Always keep your mind open to new ideas and development, and have vision as were the world is heading and try to be there before others.Do NOT forget the “environment”.Be a team player.Always be a dignified Engineer, respect yourself and other people’s dignity.Be just to yourself and give justice to others.Always Have good intentions with your thinking, actions and speaking. THANK YOU

101. 101References[1] Michael J. S. Smith, “Application-Specific Integrated Circuits,” Addison Wesley ISBN 0-201-50022-1[2] Xilinx Handbook[3] ACTEL Handbook[4] Rose J. et al. “ A classification and survey of field programmable gate array architectures,” Proceedings of The IEEE, vol. 81,no. 7 1993[5] Brown. S. et al, Field Programmable Gate Arrays. Kluwer Academic 1992 ISBN 0-7923-9248-5

102. 102 General Architecture of Xilinx FPGAs I/O BlockVertical Routing ChannelConfigurableLogic BlockHorizontalRouting ChannelFPGAs....

103. 103Basic logic cells CLBs(Configurable Logic Blocks) are bigger and more complex than the Actel or Quick Logic cells. The Xilinx LCA basic cell is an example of a coarse grain architecture that has both combinational logic and Flip Flop (FF).The XC3000 has five logic inputs, as common clock, FF, MUXs,……Using programmable MUXs connected to the SRAM programming cells, outputs of two CLBs X and Y can been independently connected to the outputs of FF Qx and Qy or to the outputs of the Combinational Logic F & G.A 32-bit Look Up Table (LUT) stored in 32 bits of SRA, provides the ability to implement combinational logic. If 5-input AND is being implemented for e.g. F = ABCDE. The content of LUT cell number 31 in the 32-bit SRAM is then set to ‘1’ and all other SRAM cells are set to ‘0’. When the input variables are applied it will act as a 5-input AND. This means that the CLBpropagation delay is fixed equal to the SRAM Access time.Xilinx LCA (Logic Cell Array)

104. 104Xilinx Design Flow

105. 105There are seven inputs in XC3000 CLB, the 5 inputs AE and the FF outputs.LUT can be broken into two halves and two functions of four variables each can be implemented Instead. Two of the inputs can be chosen from 5 CLB inputs (A-E) and then one function output connects to F and the other output connects to G.There are other methods of splitting the LUTXilinx LCA (Logic Cell Array)....

106. 106Extra Circuitry in FPGA logic blockD QSelectClockFlip-flopLUTIn1In2In3ABCF00000010010001101000101011001111LUT....

107. 107The LUT can generate any function of up to four variables or anytwo functions of three variables. Outputs can be also registered.D QABCDInputsLook-upTableOutputsYXClockUser DefinedMultiplexersSRLUT….

108. 108CLBCLBCLBCLB *CLBCLBSwitchmatrixSwitchmatrixLong LinesConnection to CLB not shown for clarityGeneral PurposeInterconnectDirectInterconnectSwitchmatrixXC2000 Interconnect