pzv0006auburnedu Vishwani D AgrawaL vagrawalengauburnedu Auburn University Dept of ECE Auburn AL 36849 USA 26 th International Conference on VLSI Design Pune India January 7 2013 ID: 247206
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Praveen Venkataramanipzv0006@auburn.edu Vishwani D. AgrawaLvagrawal@eng.auburn.eduAuburn University, Dept. of ECEAuburn, AL 36849, USA26th International Conference on VLSI Design Pune, India, January 7, 2013
Reducing Test Time of Power Constrained Test by Optimal Selection of
Supply VoltageSlide2
OutlineIntroductionProblem statementEffects of reducing power supplyPower and structure constrained testsAnalyzing power constrained testAnalyzing structure constrained testFinding an optimum test voltageResultsConclusion1/7/2013
VLSI Design"2012
2Slide3
IntroductionSignal transitions of scan ATPG patterns are higher than those of functional patternsCause high power dissipation during scan shift and capturePeak power dissipation - IR drop failures Average power dissipation – Excessive heatingPower Constraint TestLimit the maximum scan test cycle power to the allowable peak power
Slow down clock
Generate or modify vector and scan structure to reduce activity
Increased test time
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VLSI Design"2012
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Problem StatementLimit maximum test power to the allowable peak powerReduce scan test time Proposed methodologyReduce supply voltage to reduce power dissipation during testIncrease test clock frequency such that power dissipation meets the specificationFind the optimum voltage that allows the maximum power-constrained clock frequency for test
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VLSI Design"2012
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Reducing Supply VoltageAdvantagesReduced test timeCertain defects are more profound at lower voltages Resistive bridge faultPower supply noise reducesConcerns to be investigated in the futureIncreased the critical path delayPossible changes in critical paths
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VLSI Design"2012
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Power and Structure Constrained TestsPower ConstraintScan based test power dissipation can be more than functional power dissipationThe maximum power dissipated by the test is limited by the maximum allowable power for the test.Maximum activity test cycle determines the test clock frequencyStructure ConstraintClock frequency is determined by the critical path delayFastest test/functional clock period cannot
be smaller than the critical path
delay to
avoid timing
violation
Test
at lower voltages
tends to become
structure
constrainedTrade Off Slower clock
⇒
Less power
⇒ Longer test time
Faster clock
⇒
Higher power
⇒ Shorter test time
1/7/2013
VLSI Design"2012
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Power and Structure Constrained TestsCourtesy: ITC Elevator Talk Reduced Voltage Test Can be Faster! by Vishwani Agrawal
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VLSI Design"2012
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Analysis of Power constrained testThe minimum test clock period for a set of ATPG test clock cycles is limited by the maximum allowable powerQuantitatively :
w
here
T
POWER
is the power constrained test clock period,
E
MAXtest
is the maximum energy dissipated by the test
P
MAXfunc
is the maximum allowable power
T
POWER
is a function of voltage
Now, the total test time is then given by
w
here
, is the number of clock cycles.
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VLSI Design"2012
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Analysis of Power constrained test1/7/2013VLSI Design"20129Slide10
Analysis of Structure Constrained TestCritical path delay of a circuit can be approximated using α-power law model
Where
T
STRUCTURE
is the critical path delay of the CUT
V
DD
is the supply voltage
V
TH
is the threshold voltage
K
is the proportionality constant
dependent
on the critical path
α
is the velocity saturation index
Decrease in
V
DD
increases
delay
Total test time is given by
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VLSI Design"2012
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Analysis of Structure Constrained TestAssumptions:Critical path does not change as voltage is reduced; found valid for small voltage changesThreshold voltage remains constant1/7/2013VLSI Design"2012
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Analysis of Structure Constrained Test1/7/2013VLSI Design"201212Slide13
Optimum Test TimePutting it all togetherTest time for power constrained test can be reduced by reducing the supply voltageCritical path delay increases with reduction in supply voltage
Optimum test time for power constrained test
is
the point at which the test
clock runs
fastest while
the operation is still
power
constrained;
Power and structure-constrained test times are obtained analytically
Cross
point
gives the optimum
voltage and test time,
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VLSI Design"2012
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Optimum Test Time1/7/2013VLSI Design"201214Slide15
Results: Test Time OptimizationCUT
No. of Vectors
Scan cycles
Peak power
(µW)
Nominal
Voltage, 1.8V
Optimum Voltage
Test Time Reduction (%)
Test
freq. MHz
Test Time
(µs)
Supply
Voltage
(volts)
Test
Freq. (MHz)
Test Time
(µs)
s298
33
498
0.0012
187
2.7
1.04
500
0.996
62.5
s382
31
704
0.0029
300
2.3
1.35
563
1.25
46.5
s713
44
809
0.0027
136
5.9
1.45
263
3.07
48.0
s1423
62
4649
0.0045
141
33.0
1.70
158
29.42
11.0
s13207
121
41266
0.0213
110
375.0
1.45
165
250.0
40.3
s15850
125676240.1781182371.61.65222304.618.0s384171231815360.07371221491.91.501751036.130.5s385841441861590.11061291443.11.30187995.531.0
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ConclusionWhat we have achievedOptimum test time for power constrained testOptimum voltage and frequency for power constrained testsFuture explorationsConsideration of separate critical paths for scan and functional logicDelay testing at reduced voltageAdaptive dynamic power supplyDynamic test frequency (asynchronous testing)1/7/2013
VLSI Design"2012
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