PPT-Banshee: Bandwidth-Efficient DRAM Caching via Software/Hardware Cooperation

Xiangyao Yu 1 Christopher Hughes 2 Nadathur Satish 2 Onur Mutlu 3 Srinivas Devadas 1 1 MIT 2 Intel Labs 3 ETH Zürich Motivation Inpackage DRAM has . Caching Compiler Choices int x32512 forj 0 j 512 j fori 0 i 32 i xij 2xij1 int x32512 fori 0 i 32 i forj 0 j 512 j xij 2xij1 brPage 14br Caches and Consistency IO using caches Interferes with CPU may throw useful blocks IO using main m Gigascale. DRAM caches. Chiachen Chou, Georgia Tech. Aamer. . Jaleel. , NVIDIA*. Moinuddin. K. . Qureshi. , Georgia Tech. ISCA 2015. Portland, OR. June 15 , 2015. 3D DRAM Helps Mitigate Bandwidth WALL. A “Java Fun For Everyone” Interactive Quiz. What is hardware?. A program to process words. A physical component of a computer. A database of facts. A computer programming book. Question 1. What is hardware?. Fire AlarmsFlashDome Banshee ExcelTM The Banshee Excelrange of sounders, beacons, sounder beacons andcombined units and dedicated beacons available on the market today.All sounders and sounder beacons Kshitij. Sudan. , . Niladrish. . Chatterjee. , David . Nellans. , Manu . Awasthi. , Rajeev . Balasubramonian. , Al Davis. School of Computing, University of Utah. ASPLOS-2010. DRAM Memory Constraints. Codesign. of RSA for Optimal. Performance vs. Flexibility Trade-off. Malik Umar Sharif, . Rabia. . Shahid. , . Marcin . Rogawski. , and . Kris . Gaj. George Mason University. USA. Supported in part by. OLTP on NVM:. YMMV. The Last Six Months. ?. PDL Retreat. October 2013. PDL Visit Day. May 2014. Prison Life. Washing Dishes. Not Fighting. Repentant. Cafeteria Thievery. Shankings. Making . Pruno. GOOD. Network for Routing. Real-Time Multimedia. Name: Oluwaseyi Oginni. Faculty of Computing, Engineering and The Built . Environment. Birmingham City University.. Introduction. Software-defined network for professional real-time Audio and Video transmission over TCP/IP networks. High-Bandwidth, Energy-efficient DRAM Architectures for GPU systems. GPUs Demand High DRAM Bandwidth. GPUs Demand High DRAM Bandwidth. 2008: NVIDIA Tesla GT200. 512-bits @ 2.2 . Gbps. GPUs Demand High DRAM Bandwidth. Improving 3D-Stacked Memory Bandwidth at Low Cost. Donghyuk Lee, . Saugata Ghose. ,. Gennady . Pekhimenko. , Samira Khan, . Onur. . Mutlu. Carnegie Mellon University. HiPEAC. 2016. cell array. peripheral logic. Haonan. Wang, Fan Luo, . Mohamed Ibrahim. . (College of William and Mary), . Onur. . Kayiran. (AMD), . Adwait Jog (College of William and Mary). Single-Application Execution on GPUs. 2. GPU. Kernel-1 (K1). Vinson Young. Prashant Nair. Moinuddin Qureshi. 1. MOORE’s LAW HITS BANDWIDTH WALL. 2. Moore’s scaling encounters Bandwidth Wall. 3D-DRAM MITIGATES BANDWIDTH WALL. 3. 3D-DRAM. Hybrid Memory Cube (HMC) from Micron, . Guri. . Sohi. University of Wisconsin-Madison. Celebrating Yale@75. September 19, 2014. Outline. Where have we come from . Where are we are likely going. 2. Where From: Hardware. Primary goal was performance.