PPT-DICE: Compressing DRAM Caches for Bandwidth and Capacity

Vinson Young Prashant Nair Moinuddin Qureshi 1 MOOREs LAW HITS BANDWIDTH WALL 2 Moores scaling encounters Bandwidth Wall 3DDRAM MITIGATES BANDWIDTH WALL 3 3DDRAM Hybrid Memory Cube HMC from Micron . The Financial Services Forum is a source of current information and commentary about critical issues facing the industry in Boston and at the national level as well as the health of financial services in gene UDO5736157347573473OHDVH57347YLVLW57347W Gigascale. DRAM caches. Chiachen Chou, Georgia Tech. Aamer. . Jaleel. , NVIDIA*. Moinuddin. K. . Qureshi. , Georgia Tech. ISCA 2015. Portland, OR. June 15 , 2015. 3D DRAM Helps Mitigate Bandwidth WALL. by Parallelizing Refreshes. with Accesses. Donghyuk. Lee, . Zeshan. . Chishti. , . Alaa. . Alameldeen. , Chris Wilkerson, . Yoongu. Kim, . Onur. . Mutlu. Kevin Chang. Executive Summary. DRAM . refresh interferes with memory accesses. Niladrish. . Chatterjee. Manjunath. . Shevgoor. Rajeev . Balasubramonian. Al Davis. Zhen Fang. ‡†. Ramesh . Illikkal. *. Ravi . Iyer. *. University of Utah , NVidia. ‡. and Intel Labs*. †. Ph.D. Thesis Proposal. Kshitij Sudan. Thesis Statement. Improving DRAM access latency, power consumption, and capacity by leveraging intelligent data placement.. Overview. CPU. MC. DIMM. …. Todd W. Neller. Dept. of Computer Science. Dudo. “According to legend, King Atahualpa of the Incas taught this to the Spanish conquistador Pizarro more than 400 years ago…” (Mohr, 1997). Origin generally believed to be 15. Cache overview. 4 Hierarchy questions. More on Locality. Please bring these slides to the next lecture!. Projects 2 and 3. Regrade. issues for 3. Please resubmit and come to office hours with a diff.. ___________________________________________________________. Kyle Rheiner, Insurance Producer. Strickler Insurance Agency, Lebanon PA. www.CraftBrewingInsurance.com. Acknowledgement . __________________________________________________________. Access Locality. Hasan Hassan,. Gennady . Pekhimenko. , . Nandita Vijaykumar, . Vivek. . Seshadri. , Donghyuk Lee, Oguz Ergin, . Onur. . Mutlu. Executive Summary. Goal. : . Reduce average DRAM access latency with no modification to the existing DRAM chips. 2014. 11/21/2014. © 2014 DE DIOS & ASSOCIATES. ALL RIGHTS RESERVED. Reproduction prohibited without prior permission.. 1. DRAM market entering a new phase – a more “normal” market – in 2015. Xiangyao. Yu. 1. , Christopher Hughes. 2. , . Nadathur. Satish. 2. , . Onur. Mutlu. 3. , Srinivas . Devadas. 1. 1. MIT . 2 . Intel Labs . 3. ETH Zürich. Motivation. In-package DRAM has . �� �� Roll Around the Clock 3 players) 2 dice Make a clock face numbered 1 through 12. Players take turns rolling two dice and adding them to How to play Each player places the extra die before him or her on the table with the 6 face up Decide who starts the turn order then proceeds clockwise You play several rounds and in each round t Vivek Seshadri. Thomas Mullins, . Amirali. . Boroumand. , Onur Mutlu, . Phillip B. . Gibbons, Michael A. Kozuch, . Todd C. Mowry. Executive summary. Problem: Non-unit . strided. accesses. Present in many applications.