PPT-Improving DRAM Performance

Author : trish-goza | Published Date : 2015-09-26

by Parallelizing Refreshes with Accesses Donghyuk Lee Zeshan Chishti Alaa Alameldeen Chris Wilkerson Yoongu Kim Onur Mutlu Kevin Chang Executive Summary

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Improving DRAM Performance: Transcript


by Parallelizing Refreshes with Accesses Donghyuk Lee Zeshan Chishti Alaa Alameldeen Chris Wilkerson Yoongu Kim Onur Mutlu Kevin Chang Executive Summary DRAM refresh interferes with memory accesses. Gigascale. DRAM caches. Chiachen Chou, Georgia Tech. Aamer. . Jaleel. , NVIDIA*. Moinuddin. K. . Qureshi. , Georgia Tech. ISCA 2015. Portland, OR. June 15 , 2015. 3D DRAM Helps Mitigate Bandwidth WALL. Penn State . DAC’12, ISPASS’13. Architecture Reading Club Spring'13. 1. Cache-Revive: Architecting Volatile STT-RAM Caches for Enhanced Performance in CMPs. Penn State . DAC’12. Architecture Reading Club Spring'13. Jaewoong. . Sim. *, Gabriel H. Loh. +. , Vilas Sridharan. #. , Mike O’Connor. +. June . 2013 . *Georgia Tech. +. AMD Research. #. AMD RAS Architecture. Die-stacked Memory. Die-stacking is coming along, esp. DRAM. In-DRAM Address Translation to Improve the Spatial Locality of Non-unit Strided Accesses. Vivek Seshadri. Thomas Mullins, . Amirali. . Boroumand. , Onur Mutlu, . Phillip B. . Gibbons, Michael A. Kozuch, . Niladrish. . Chatterjee. Manjunath. . Shevgoor. Rajeev . Balasubramonian. Al Davis. Zhen Fang. ‡†. Ramesh . Illikkal. *. Ravi . Iyer. *. University of Utah , NVidia. ‡. and Intel Labs*. †. Kshitij. Sudan. , . Niladrish. . Chatterjee. , David . Nellans. , Manu . Awasthi. , Rajeev . Balasubramonian. , Al Davis. School of Computing, University of Utah. ASPLOS-2010. DRAM Memory Constraints. DRAM Scaling. Prof. Onur Mutlu. http://www.ece.cmu.edu/~omutlu. onur@cmu.edu. HiPEAC. ACACES Summer School 2013. July 15-19, . 2013. The Main Memory System. Main memory is a critical component of all computing systems. Low-Power High-Performance Computing. Jie. Meng, Daniel . Rossell. , and . Ayse. K. . Coskun. Performance and Energy Aware Computing Lab (PEAC-Lab). Electrical and Computer Engineering Department. Boston University. Xianwei Zhang. Youtao. Zhang (advisor). CS, Pitt. Bruce R. Childers. CS, Pitt. Wonsun. . Ahn. CS, Pitt. Jun Yang. ECE, Pitt. Guangyong. Li. ECE, Pitt. Committees: . PhD Thesis . Defense. Jul 14, 2017 (Friday). Access Locality. Hasan Hassan,. Gennady . Pekhimenko. , . Nandita Vijaykumar, . Vivek. . Seshadri. , Donghyuk Lee, Oguz Ergin, . Onur. . Mutlu. Executive Summary. Goal. : . Reduce average DRAM access latency with no modification to the existing DRAM chips. 2014. 11/21/2014. © 2014 DE DIOS & ASSOCIATES. ALL RIGHTS RESERVED. Reproduction prohibited without prior permission.. 1. DRAM market entering a new phase – a more “normal” market – in 2015. by Exploiting the Variation in Local . Bitlines. . Jeremie S. Kim. . Minesh. Patel . Hasan Hassan . Onur. . Mutlu. . Motivation. : DRAM latency is a . major performance bottleneck. Problem. Big Data Processing over Hybrid Memories. Chenxi Wang. Huimin Cui. Ting Cao. John . Zigman. Haris Volos. Onur . Mutlu. Fang . Lv. Xiaobing Feng. Guoqing Harry Xu. Big. . Data. . Workloads. MLlib. Current. Unclonable. Functions . by Exploiting the Latency-Reliability Tradeoff . in Modern Commodity DRAM Devices. Jeremie. S. Kim. . Minesh. Patel . Hasan Hassan . . Onur. . Mutlu. . Motivation.

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