PPT-Scalable Many-Core Memory Systems Topic 1: DRAM Basics and

DRAM Scaling Prof Onur Mutlu httpwwwececmueduomutlu onurcmuedu HiPEAC ACACES Summer School 2013 July 1519 2013 The Main Memory System Main memory is a critical component of all computing systems. Niladrish. . Chatterjee. Manjunath. . Shevgoor. Rajeev . Balasubramonian. Al Davis. Zhen Fang. ‡†. Ramesh . Illikkal. *. Ravi . Iyer. *. University of Utah , NVidia. ‡. and Intel Labs*. †. Prashant. Nair. Chia-Chen Chou . Moinuddin Qureshi. 1. Dynamic Random Access Memory (DRAM) used as main memory. DRAM stores data as charge on capacitor. Leakage. DRAM cells leak data!. DRAM Chip. 1. Ted . Huffmire. ACACES 2012. Fiuggi. , Italy. Disclaimer. The views presented in this course are those of the speaker and do not necessarily reflect the views of the United States Department of Defense.. 2010 Turing Award Recipient. Chuck Thacker. Improving the future by examining the past. Thesis. Computer architecture has hit a wall.. This will require us to build future systems in new ways.. New systems will require changes in the way we program them.. Prashant. Nair. Chia-Chen Chou . Moinuddin Qureshi. 1. Dynamic Random Access Memory (DRAM) used as main memory. DRAM stores data as charge on capacitor. Leakage. DRAM cells leak data!. DRAM Chip. 1. University . of Illinois, 2007-2012. CS/EE 217. GPU Architecture and Parallel Programming. Lecture . 6: . DRAM Bandwidth. 1. Objective. To understand DRAM bandwidth. Cause of the DRAM bandwidth problem. Low-Power High-Performance Computing. Jie. Meng, Daniel . Rossell. , and . Ayse. K. . Coskun. Performance and Energy Aware Computing Lab (PEAC-Lab). Electrical and Computer Engineering Department. Boston University. 1. , Jose F. Martinez. 2. , Rich Caruana. 2. Self-Optimizing Memory Controllers: . A . Reinforcement . Learning Approach. 1. Microsoft Research. . 2. Cornell University. . 1. Riding Moore’s Law with CMPs. Sep 17, 2017. COMPUTER ARCHITECTURE . CS 6354. Main Memory. The content and concept of this course are adapted from CMU ECE 740. AGENDA. Logistics. Review . from last . lecture. Main Memory. 2. LOGISTICS. and the Implications for Performance Optimization. Samuel Williams. 1,2. Jonathan Carter. 2. , Richard Vuduc. 3. , Leonid Oliker. 1,2. , John Shalf. 2. , . Katherine Yelick. 1,2. , James Demmel. 1,2. Manu Awasthi , . David Nellans. , Kshitij Sudan, . Rajeev Balasubramonian, Al Davis. University of Utah. Takeaway. Multiple, on-chip MCs will be common in future CMPs, with multiple cores sharing one MC. Prof. Onur Mutlu. ETH Zürich. Fall 2019. 27 September 2019. Solving the Memory Problem. Fix it. : Make memory and controllers more intelligent. New interfaces, functions, architectures. : system-. mem. Mar 3, 2016. COMPUTER ARCHITECTURE . CS 6354. Main Memory. The content and concept of this course are adapted from CMU ECE 740. AGENDA. Logistics. Review . from last . lecture. Main Memory. 2. ANONYMOUS FEEDBACK.