PPT-Optimizing DRAM Based Main Memories Using Intelligent Data

Author : danika-pritchard | Published Date : 2015-11-20

PhD Thesis Proposal Kshitij Sudan Thesis Statement Improving DRAM access latency power consumption and capacity by leveraging intelligent data placement Overview

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Optimizing DRAM Based Main Memories Using Intelligent Data: Transcript

PhD Thesis Proposal Kshitij Sudan Thesis Statement Improving DRAM access latency power consumption and capacity by leveraging intelligent data placement Overview CPU MC DIMM . Bank Privatization for Predictability and Temporal Isolation. Sungjun. . Kim . Columbia . University. Edward A. Lee . UC . Berkeley . Isaac . Liu . UC Berkeley. Hiren. D. Patel University of Waterloo. Fraud Investigations in Louisiana Department of Children and Families (DCFS). Ted deSaussure. Optimizing Performance in Volatile Times. Background. Large scale fraud investigation conducted in New Orleans involving Secret Service, multiple Federal law enforcement agencies & LA DCFS. DRAM Scaling. Prof. Onur Mutlu. http://www.ece.cmu.edu/~omutlu. onur@cmu.edu. HiPEAC. ACACES Summer School 2013. July 15-19, . 2013. The Main Memory System. Main memory is a critical component of all computing systems. How are these pictures connected?. Think back to the Teleological Argument (Synoptic link). Intelligent Design (ID) . argues that everything on earth . has the appearance of . design. . . Therefore there must be an . 1. , Jose F. Martinez. 2. , Rich Caruana. 2. Self-Optimizing Memory Controllers: . A . Reinforcement . Learning Approach. 1. Microsoft Research. . 2. Cornell University. . 1. Riding Moore’s Law with CMPs. Big Data Analytics. Sang-Woo Jun. *. Ming Liu. *. . Sungjin. Lee. *. Jamey Hicks. . John . Ankcorn. . Myron King. . . Shuotao. Xu. *. Arvind. *. *. MIT Computer Science and Artificial Intelligence Laboratory. Intelligent techniques for enhancing decision making. Many based on a. rtificial intelligence (AI). C. omputer-based systems (hardware and software) that attempt to emulate human behavior and thought patterns. Access Locality. Hasan Hassan,. Gennady . Pekhimenko. , . Nandita Vijaykumar, . Vivek. . Seshadri. , Donghyuk Lee, Oguz Ergin, . Onur. . Mutlu. Executive Summary. Goal. : . Reduce average DRAM access latency with no modification to the existing DRAM chips. 2014. 11/21/2014. © 2014 DE DIOS & ASSOCIATES. ALL RIGHTS RESERVED. Reproduction prohibited without prior permission.. 1. DRAM market entering a new phase – a more “normal” market – in 2015. 2014. 9/30/2014. © 2014 DE DIOS & ASSOCIATES. ALL RIGHTS RESERVED. Reproduction prohibited without prior permission.. 1. Strange situation: demand is weakening while supply remains tight. Weakening PC-DRAM demand and supply mix issues in 2H14. Vinson Young. Prashant Nair. Moinuddin Qureshi. 1. MOORE’s LAW HITS BANDWIDTH WALL. 2. Moore’s scaling encounters Bandwidth Wall. 3D-DRAM MITIGATES BANDWIDTH WALL. 3. 3D-DRAM. Hybrid Memory Cube (HMC) from Micron, . Xiangyao. Yu. 1. , Christopher Hughes. 2. , . Nadathur. Satish. 2. , . Onur. Mutlu. 3. , Srinivas . Devadas. 1. 1. MIT . 2 . Intel Labs . 3. ETH Zürich. Motivation. In-package DRAM has . Mar 3, 2016. COMPUTER ARCHITECTURE . CS 6354. Main Memory. The content and concept of this course are adapted from CMU ECE 740. AGENDA. Logistics. Review . from last . lecture. Main Memory. 2. ANONYMOUS FEEDBACK. Unclonable. Functions . by Exploiting the Latency-Reliability Tradeoff . in Modern Commodity DRAM Devices. Jeremie. S. Kim. . Minesh. Patel . Hasan Hassan . . Onur. . Mutlu. . Motivation.

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