PPT-Optimizing DRAM Based Main Memories Using Intelligent Data

Author : danika-pritchard | Published Date : 2015-11-20

PhD Thesis Proposal Kshitij Sudan Thesis Statement Improving DRAM access latency power consumption and capacity by leveraging intelligent data placement Overview

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Optimizing DRAM Based Main Memories Using Intelligent Data: Transcript

PhD Thesis Proposal Kshitij Sudan Thesis Statement Improving DRAM access latency power consumption and capacity by leveraging intelligent data placement Overview CPU MC DIMM . Caching Compiler Choices int x32512 forj 0 j 512 j fori 0 i 32 i xij 2xij1 int x32512 fori 0 i 32 i forj 0 j 512 j xij 2xij1 brPage 14br Caches and Consistency IO using caches Interferes with CPU may throw useful blocks IO using main m Niladrish. . Chatterjee. Manjunath. . Shevgoor. Rajeev . Balasubramonian. Al Davis. Zhen Fang. ‡†. Ramesh . Illikkal. *. Ravi . Iyer. *. University of Utah , NVidia. ‡. and Intel Labs*. †. : . An Appliance for . Big Data Analytics. Sang-Woo Jun. *. Ming Liu. *. . Sungjin. Lee. *. Jamey Hicks. +. John . Ankcorn. +. Myron King. +. . Shuotao. Xu. *. Arvind. *. *. MIT Computer Science and Artificial Intelligence Laboratory. Jaewoong. . Sim. *, Gabriel H. Loh. +. , Vilas Sridharan. #. , Mike O’Connor. +. June . 2013 . *Georgia Tech. +. AMD Research. #. AMD RAS Architecture. Die-stacked Memory. Die-stacking is coming along, esp. DRAM. Niladrish. . Chatterjee. Manjunath. . Shevgoor. Rajeev . Balasubramonian. Al Davis. Zhen Fang. ‡†. Ramesh . Illikkal. *. Ravi . Iyer. *. University of Utah , NVidia. ‡. and Intel Labs*. †. Montek Singh. Oct 24, . 2016. Topics. Previous lecture on memories:. Read-Only Memories (ROMs). Static. Random-Access. . Memory (SRAM). Today:. Dynamic. Random. -Access . Memory (DRAM). 2. Dynamic . How are these pictures connected?. Think back to the Teleological Argument (Synoptic link). Intelligent Design (ID) . argues that everything on earth . has the appearance of . design. . . Therefore there must be an . Oct 23, 2017. COMPUTER ARCHITECTURE . CS 6354. Emerging Memory Technologies. The content and concept of this course are adapted from CMU ECE 740. AGENDA. Logistics. Review . from last . lecture. Emerging Memory Technology . 1. , Jose F. Martinez. 2. , Rich Caruana. 2. Self-Optimizing Memory Controllers: . A . Reinforcement . Learning Approach. 1. Microsoft Research. . 2. Cornell University. . 1. Riding Moore’s Law with CMPs. Sep 17, 2017. COMPUTER ARCHITECTURE . CS 6354. Main Memory. The content and concept of this course are adapted from CMU ECE 740. AGENDA. Logistics. Review . from last . lecture. Main Memory. 2. LOGISTICS. Big Data Analytics. Sang-Woo Jun. *. Ming Liu. *. . Sungjin. Lee. *. Jamey Hicks. . John . Ankcorn. . Myron King. . . Shuotao. Xu. *. Arvind. *. *. MIT Computer Science and Artificial Intelligence Laboratory. Mar 3, 2016. COMPUTER ARCHITECTURE . CS 6354. Main Memory. The content and concept of this course are adapted from CMU ECE 740. AGENDA. Logistics. Review . from last . lecture. Main Memory. 2. ANONYMOUS FEEDBACK. Prof. Onur Mutlu. Carnegie Mellon University. Main Memory Lectures. These slides are . from the . Scalable . Memory Systems. course . taught at . ACACES . 2013 (July 15-19, 2013). Course Website:. http. Lecture 7: Emerging Memory Technologies. Prof. . Onur. . Mutlu. Carnegie Mellon University. 9/21/2012. Reminder: Review Assignments. Due: Friday, September 21, 11:59pm.. Smith, “. Architecture and applications of the HEP multiprocessor computer system.

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