CPU Memory CPU CPU Memory CPU CPU Memory CPU CPU Memory CPU Memory CPU Memory Single - PDF document

Mat Laibowitzand Albert Chiou Shared Memory Architecture CPU •We want multiple processors to share memory ??????? Shared Memory Architecture CPU Single, large memoryMultiple smaller memories•Scalability•Access Time•Cost•Application: WLAN vsSingle chip multiprocessor Snooping vsDirectory CPU = M= I= I CPU = M !!! Pending-�1WriteBackPending-�0 & Pass TokenWriteBackWriteBackWrite(Miss)Add DATA; Cache-�I & PASSWrite(Hit)Read(Miss)Add DATA; Cache-�S & PASSRead(Hit)Write(Hit)Read(Hit)Pending-�0, Pass TokenWriteBackModify Cache;Cach�e-M & Pass TokenWriteWriteBackWrite(Miss)Add DATA; Cache-�I & PASSWrite(Hit)Read(Miss)Add DATA; PASSRead(Hit)Pending-�1; SEND WriteWriteRead(Hit)DATA�/M-Cache, Modify Cache;SEND WriteBack(DATA),SEND WriteBack(data),Pending-�2Write (M)I & MissDATA�/M-Cache, Modify Cache;SEND WriteBack(DATA)Write (I/S)I & MissDATA/S�-Cache;SEND WriteBack(DATA)ReadI & MissWriteBackI & MissWriteI & MissReadI & MissPending-�1; SEND WriteWriteI & MissPending-�1; SEND ReadReadI & MissActionsTransactionRingTransactionPendingStateCache State •A ring topology was chosen for speed and –Only point-to-point–Like a bus–Scaleable •Uses a token to ensure sequential Test Rig mkMSICacheController waitReg pending token ringOutFIFO ringInFIFO requestFIFO responseFIFO mkMSICache $ Controller rules mkMultiCacheTH mkMultiCache ringIn fromDMem dataReqQ dataRespQ $ Controller ringOut rule rule rule rule rule �= Cache 2: toknMsgop-�Tk8�= Cache 5: toknMsgop-�Tk2=� Cache 3: ringMsgop-�WrBkaddr-�0000022c data-�aaaaaaaavalid-�1 cache-�1=� Cache 3: getStateI=� Cache 1: newCpuReqSt { addr=00000230, data=ba4f0452 }=� Cache 1: getStateI�= Cycle = 56�= Cache 2: toknMsgop-�Tk7=� Cache 6: ringMsgop-�Rd addr-�00000250 data-�aaaaaaaavalid-�1 cache-�6=� DataMem: ringMsgop-�WrBkaddr-�00000374 data-�aaaaaaaavalid-�1 cache-�5=� Cache 6: getStateI=� Cache 8: ringReturnop-�Wraddr-�000003a8 data-�aaaaaaaavalid-�1 cache-�7=� Cache 8: getStateI=� Cache 8: writeLinestate-�M addr-�000003a8 data-�4ac6efe7=� Cache 3: ringMsgop-�WrBkaddr-�00000360 data-�aaaaaaaavalid-�1 cache-�4=� Cache 3: getStateI�= Cycle = 57�= Cache 6: toknMsgop-�Tk2�= Cache 3: toknMsgop-�Tk8=� Cache 4: ringMsgop-�WrBkaddr-�0000022c data-�aaaaaaaavalid-�1 cache-�1=� Cache 4: getStateI�= Cycle = 58=� dMemReq: St { addr=00000374, data=aaaaaaaa}�= Cache 3: toknMsgop-�Tk7=� Cache 7: ringReturnop-�Rd addr-�00000250 data-�aaaaaaaavalid-�1 cache-�6=� Cache 7: writeLinestate-�S addr-�00000250 data-�aaaaaaaa=� Cache 7: getStateI=� Cache 1: ringMsgop-�WrBkaddr-�00000374 data-�aaaaaaaavalid-�1 cache-�5=� Cache 1: getStateI=� Cache 4: ringMsgop-�WrBkaddr-�00000360 data-�aaaaaaaavalid-�1 cache-�4=� Cache 4: getStateI=� Cache 9: ringMsgop-�WrBkaddr-�000003a8 data-�aaaaaaaavalid-�1 cache-�7=� Cache 9: getStateI�= Cycle = 59=� Cache 5: ringMsgop-�WrBkaddr-�0000022c data-�aaaaaaaavalid-�1 cache-�1=� Cache 5: getStateI�= Cache 7: toknMsgop-�Tk2=� Cache 3: execCpuReqLd { addr=000002b8, tag=00 }=� Cache 3: getStateI�= Cache 4: toknMsgop-�Tk8�= Cycle = 60=� DataMem: ringMsgop-�WrBkaddr-�000003a8 data-�aaaaaaaavalid-�1 cache-�7=� Cache 2: ringMsgop-�WrBkaddr-�00000374 data-�aaaaaaaavalid-�1 cache-�5=� Cache 2: getStateI=� Cache 8: ringMsgop-�WrBkaddr-�00000250 data-�aaaaaaaavalid-�1 cache-�6=� Cache 8: getStateI=� Cache 5: ringReturnop-�WrBkaddr-�00000360 data-�aaaaaaaavalid-�1 cache-�4=� Cache 5: getStateS�= Cycle = 61�= Cache 5: toknMsgop-�Tk8 Number of Controllers vs. Avg. Access Time (2 Tokens)369Number of ControllersAverage Access Time (clock cyles) Placed and Routed •Clock speed: 3.71ns (~270 Mhz)•Area: 1,296,726 µm•Average memory access time: ~39ns