PPT-Cache Coherence: Directory Protocol

Smruti R Sarangi IIT Delhi Contents Overview of the Directory Protocol Details Optimizations Basic Idea of a Coherence Protocol Memory Level n Memory Level n2 Private Cache Private Cache. Marc De Melo. Outline. Non-Uniform Cache Architecture (NUCA). Cache Coherence. Implementation of directories in multicore architecture. 2. Non-Uniform Cache Architecture [1]. Uniform Cache Architecture. George Kurian. 1. , Omer Khan. 2. , . Srini. . Devadas. 1. 1 . Massachusetts Institute of Technology. 2 . University of Connecticut, Storrs. 1. Cache Hierarchy Organization. Directory-Based Coherence. †. : Rethinking Hardware for Disciplined Parallelism. Byn Choi, Rakesh Komuravelli, Hyojin Sung, . Rob Bocchino, Sarita Adve, Vikram Adve. Other collaborators:. Languages: Adam Welc, Tatiana Shpeisman, Yang Ni (Intel). f. or . Integrated CPU-GPU Systems. Jason Power*. , Arkaprava Basu*, . Junli. . Gu. †. , Sooraj Puthoor. †. ,. Bradford M Beckmann. †. , Mark D Hill*. †. , Steven K Reinhardt. †. , David A Wood*. Graduate Computer Architecture. Lecture 20. April . 9. th. , . 2012. Distributed Shared Memory. Prof John D. Kubiatowicz. http://www.cs.berkeley.edu/~kubitron/cs252. LD. 1. A .  5. LD. 2. B  7. †. : Rethinking Hardware for Disciplined Parallelism. Byn Choi, Rakesh Komuravelli, Hyojin Sung, . Rob Bocchino, Sarita Adve, Vikram Adve. Other collaborators:. Languages: Adam Welc, Tatiana Shpeisman, Yang Ni (Intel). Smruti R. Sarangi, IIT Delhi. Contents. Overview of the Directory Protocol. Details. Optimizations. Basic Idea of a Coherence Protocol. Memory Level . n. Memory Level . n+2. Private Cache. Private Cache. Coherence . Directories. Michael . C. . Huang. Guofan. Jiang. Zhejiang University. University . of . Rochester. IBM. 1. Lei Fang. , . Peng. Liu, and Qi Hu. Motivation. 2. Technology scaling has steadily increased the number . Systems. Distributed Shared Memory. Prof. Chung-Ta King. Department of Computer Science. National Tsing Hua University, Taiwan. (Slides are from textbook, . Prof. . O. . Mutlu. , Prof. . Hsien-Hsin. Lee. f. or . Integrated CPU-GPU Systems. Jason Power*. , Arkaprava Basu*, . Junli. . Gu. †. , Sooraj Puthoor. †. ,. Bradford M Beckmann. †. , Mark D Hill*. †. , Steven K Reinhardt. †. , David A Wood*. :. What is Cache Coherence?. Cache Coherence: Do we need it? . Coherence Property - I:. Read R from Address X on Core C0 returns the value written by the most recent write W on X on C0, if no other core has written to X between W and R.. 2. Educational objectives The MESI protocol simulator is widely used in several courses about Computer Architecture, Computer Design and Multiprocessor Systems in the University of Cordoba. The syllab Multicore . Memory. . Hierarchy for. . Disciplined Parallelism. Byn. Choi. , . Nima. . Honarmand. , . Rakesh Komuravelli. , . Robert . Smolinski. , . Hyojin Sung. , Sarita V. . Adve. , . Vikram. S. . Lecture 20. April . 9. th. , . 2012. Distributed Shared Memory. Prof John D. Kubiatowicz. http://www.cs.berkeley.edu/~kubitron/cs252. LD. 1. A .  5. LD. 2. B  7. LD. 5. B .  2. ST. 1. A,6.