PPT-Cache Coherence: Directory Protocol

Smruti R Sarangi IIT Delhi Contents Overview of the Directory Protocol Details Optimizations Basic Idea of a Coherence Protocol Memory Level n Memory Level n2 Private Cache Private Cache. Autumn 2006 CSE P548 Cache Coherence 6 A Lowend MP brPage 4br Autumn 2006 CSE P548 Cache Coherence 7 Cache Coherency Prot ocol Implementations Snooping used with lowend MPs few processors centralized memory busbased distributed implementation Marc De Melo. Outline. Non-Uniform Cache Architecture (NUCA). Cache Coherence. Implementation of directories in multicore architecture. 2. Non-Uniform Cache Architecture [1]. Uniform Cache Architecture. †. : Rethinking Hardware for Disciplined Parallelism. Byn Choi, Rakesh Komuravelli, Hyojin Sung, . Rob Bocchino, Sarita Adve, Vikram Adve. Other collaborators:. Languages: Adam Welc, Tatiana Shpeisman, Yang Ni (Intel). Tomas . Mancal. Charles University in Prague. QuEBS. 09. 8.7.2009 Lisbon. Collaborators. : . Jan . Ol. šina, . Vytautas. . Balevičius. . and. . Leonas. . Valkunas. System of Interest: Photosynthetic Aggregates of Chlorophylls. f. or . Integrated CPU-GPU Systems. Jason Power*. , Arkaprava Basu*, . Junli. . Gu. †. , Sooraj Puthoor. †. ,. Bradford M Beckmann. †. , Mark D Hill*. †. , Steven K Reinhardt. †. , David A Wood*. CS448. 2. What is Cache Coherence?. Two processors can have two different values for the same memory location. Write Through Cache. 3. Terminology. Coherence. Defines what values can be returned by a read. AMANO, Hideharu, Keio University. hunga@am. ．. ics. ．. keio. ．. ac. ．. jp. Textbook. 　. pp.40-60. Cache memory. A small high speed memory for storing frequently accessed data/instructions.. f. or . Integrated CPU-GPU Systems. Jason Power*. , Arkaprava Basu*, . Junli. . Gu. †. , Sooraj Puthoor. †. ,. Bradford M Beckmann. †. , Mark D Hill*. †. , Steven K Reinhardt. †. , David A Wood*. :. What is Cache Coherence?. When one Core writes to its own cache the other core gets to see it, when they read it out of its own cache.. Provides underlying guarantees for the programmer with respect to data validation.. wrt. . . Trace Filters. Parosh. . Aziz Abdulla. 1. , . Mohamed . Faouzi. Atig. 1. , . Zeinab. Ganjei. 2. , Ahmed Rezine. 2. . and . Yunyun. . Zhu. 1. 1. Uppsala. . University, Sweden. 2. . Lin. wrt. . . Trace Filters. Parosh. . Aziz Abdulla. 1. , . Mohamed . Faouzi. Atig. 1. , . Zeinab. Ganjei. 2. , Ahmed Rezine. 2. . and . Yunyun. . Zhu. 1. 1. Uppsala. . University, Sweden. 2. . Lin. sharedmemory architectures Adapted from a lecture by Ian Watson, University of Machester Overview We have talked about optimizing performance on single coresLocalityVectorizationNow let us look at opt 2. Educational objectives The MESI protocol simulator is widely used in several courses about Computer Architecture, Computer Design and Multiprocessor Systems in the University of Cordoba. The syllab Multicore . Memory. . Hierarchy for. . Disciplined Parallelism. Byn. Choi. , . Nima. . Honarmand. , . Rakesh Komuravelli. , . Robert . Smolinski. , . Hyojin Sung. , Sarita V. . Adve. , . Vikram. S. .