PPT-Cache Coherence: Directory Protocol

Smruti R Sarangi IIT Delhi Contents Overview of the Directory Protocol Details Optimizations Basic Idea of a Coherence Protocol Memory Level n Memory Level n2 Private Cache Private Cache. Message Passing Sharedmemory single copy of shared data in memory threads communicate by readingwriting to a shared location Messagepassing each thread has a copy of data in its own private memory that other threads cannot access threads communicate Autumn 2006 CSE P548 Cache Coherence 6 A Lowend MP brPage 4br Autumn 2006 CSE P548 Cache Coherence 7 Cache Coherency Prot ocol Implementations Snooping used with lowend MPs few processors centralized memory busbased distributed implementation George Kurian. 1. , Omer Khan. 2. , . Srini. . Devadas. 1. 1 . Massachusetts Institute of Technology. 2 . University of Connecticut, Storrs. 1. Cache Hierarchy Organization. Directory-Based Coherence. †. : Rethinking Hardware for Disciplined Parallelism. Byn Choi, Rakesh Komuravelli, Hyojin Sung, . Rob Bocchino, Sarita Adve, Vikram Adve. Other collaborators:. Languages: Adam Welc, Tatiana Shpeisman, Yang Ni (Intel). -Client Pairing: A Framework for Implementing Coherence Hierarchies. Jesse G. Beu. Michael C. Rosier. Thomas M. Conte. Tinker Research. Georgia Institute . of Technology. The Problem. Coherence protocols can be difficult to design properly. Julia Hirschberg. CS 4705. Thanks to Dan Jurafsky, Diane Litman, Andy Kehler, Jim Martin . What makes a text or dialogue coherent? . “Consider, for example, the difference between passages (18.71) and (18.72). Almost certainly not. The reason is that these utterances, when juxtaposed, will not exhibit coherence. Do you have a discourse? Assume that you have collected an arbitrary set of well-formed and independently interpretable utterances, for instance, by randomly selecting one sentence from each of the previous chapters of this book.” . CS448. 2. What is Cache Coherence?. Two processors can have two different values for the same memory location. Write Through Cache. 3. Terminology. Coherence. Defines what values can be returned by a read. †. : Rethinking Hardware for Disciplined Parallelism. Byn Choi, Rakesh Komuravelli, Hyojin Sung, . Rob Bocchino, Sarita Adve, Vikram Adve. Other collaborators:. Languages: Adam Welc, Tatiana Shpeisman, Yang Ni (Intel). (. Chapter 8) . Ken Koedinger. 1. Coherence Principle. Which is better for student learning?. A. When extraneous, entertaining material is included. B. When extraneous, entertaining material is excluded. :. What is Cache Coherence?. When one Core writes to its own cache the other core gets to see it, when they read it out of its own cache.. Provides underlying guarantees for the programmer with respect to data validation.. wrt. . . Trace Filters. Parosh. . Aziz Abdulla. 1. , . Mohamed . Faouzi. Atig. 1. , . Zeinab. Ganjei. 2. , Ahmed Rezine. 2. . and . Yunyun. . Zhu. 1. 1. Uppsala. . University, Sweden. 2. . Lin. wrt. . . Trace Filters. Parosh. . Aziz Abdulla. 1. , . Mohamed . Faouzi. Atig. 1. , . Zeinab. Ganjei. 2. , Ahmed Rezine. 2. . and . Yunyun. . Zhu. 1. 1. Uppsala. . University, Sweden. 2. . Lin. sharedmemory architectures Adapted from a lecture by Ian Watson, University of Machester Overview We have talked about optimizing performance on single coresLocalityVectorizationNow let us look at opt 2. Educational objectives The MESI protocol simulator is widely used in several courses about Computer Architecture, Computer Design and Multiprocessor Systems in the University of Cordoba. The syllab