PPT-The Locality-Aware Adaptive Cache Coherence Protocol

George Kurian 1 Omer Khan 2 Srini Devadas 1 1 Massachusetts Institute of Technology 2 University of Connecticut Storrs 1 Cache Hierarchy Organization DirectoryBased Coherence. †. : Rethinking Hardware for Disciplined Parallelism. Byn Choi, Rakesh Komuravelli, Hyojin Sung, . Rob Bocchino, Sarita Adve, Vikram Adve. Other collaborators:. Languages: Adam Welc, Tatiana Shpeisman, Yang Ni (Intel). -Client Pairing: A Framework for Implementing Coherence Hierarchies. Jesse G. Beu. Michael C. Rosier. Thomas M. Conte. Tinker Research. Georgia Institute . of Technology. The Problem. Coherence protocols can be difficult to design properly. Graduate Computer Architecture. Lecture 20. April . 9. th. , . 2012. Distributed Shared Memory. Prof John D. Kubiatowicz. http://www.cs.berkeley.edu/~kubitron/cs252. LD. 1. A .  5. LD. 2. B  7. †. : Rethinking Hardware for Disciplined Parallelism. Byn Choi, Rakesh Komuravelli, Hyojin Sung, . Rob Bocchino, Sarita Adve, Vikram Adve. Other collaborators:. Languages: Adam Welc, Tatiana Shpeisman, Yang Ni (Intel). T. Rogers, M O’Conner, and T. . Aamodt. MICRO 2012. Goal. Understand the relationship between schedulers (warp/wavefront) and locality behaviors . Distinguish between inter-wavefront and intra-wavefront locality. Dept. of Electrical & Computer Engineering. Computer Architecture . ECE 668. Multiprocessor Systems. Csaba Andras Moritz. Textbook: Dubois, . Annavaram. , . Stenstrom. , Parallel Computer Organization and Design. Smruti R. Sarangi, IIT Delhi. Contents. Overview of the Directory Protocol. Details. Optimizations. Basic Idea of a Coherence Protocol. Memory Level . n. Memory Level . n+2. Private Cache. Private Cache. George Kurian. 1. , . Srinivas. . Devadas. 1. , Omer . Khan. 2. , . 1 . Massachusetts Institute of Technology. 2 . University of Connecticut, . Storrs. 1. The Problem. Future multicore processors will have 100s of cores. Smruti R. Sarangi, IIT Delhi. Contents. Overview of the Directory Protocol. Details. Optimizations. Basic Idea of a Coherence Protocol. Memory Level . n. Memory Level . n+2. Private Cache. Private Cache. T. Rogers, M O’Conner, and T. . Aamodt. MICRO 2012. Goal. Understand the relationship between schedulers (warp/wavefront) and locality behaviors . Distinguish between inter-wavefront and intra-wavefront locality. :. What is Cache Coherence?. Cache Coherence: Do we need it? . Coherence Property - I:. Read R from Address X on Core C0 returns the value written by the most recent write W on X on C0, if no other core has written to X between W and R.. :. What is Cache Coherence?. When one Core writes to its own cache the other core gets to see it, when they read it out of its own cache.. Provides underlying guarantees for the programmer with respect to data validation.. 2. Educational objectives The MESI protocol simulator is widely used in several courses about Computer Architecture, Computer Design and Multiprocessor Systems in the University of Cordoba. The syllab Lecture 20. April . 9. th. , . 2012. Distributed Shared Memory. Prof John D. Kubiatowicz. http://www.cs.berkeley.edu/~kubitron/cs252. LD. 1. A .  5. LD. 2. B  7. LD. 5. B .  2. ST. 1. A,6.