PPT-Locality-Aware Data Replication in the Last-Level Cache

George Kurian 1 Srinivas Devadas 1 Omer Khan 2 1 Massachusetts Institute of Technology 2 University of Connecticut Storrs 1 The Problem Future multicore processors will have 100s of cores. George Kurian. 1. , Omer Khan. 2. , . Srini. . Devadas. 1. 1 . Massachusetts Institute of Technology. 2 . University of Connecticut, Storrs. 1. Cache Hierarchy Organization. Directory-Based Coherence. Optimization. Techniques. . Presented by . Preethi Rajaram. CSS 548 Introduction to Compilers . Professor Carol Zander. Fall 2012 . Why?. Processor Speed . -. increasing at a faster rate than the memory speed. M. . Siberstein. , A. Schuster, D. Geiger, A. . Patley. , J. Owens. Introduction. MPF characterized by. Complex data dependent . High data reuse . Low compute-to-memory access ration. Technique to solve MPF . Han Wang. CS 3410, Spring . 2012. Computer Science. Cornell University. See P&H . 5.1, 5.2 (except writes. ). Announcements. This week:. PA2 Work-in-progress submission. Next six weeks:. Two labs and two projects. A General Analytical Study. Yongkun. Li, . Patrick P. C. Lee. , John C. S. . Lui. , . Yinlong. Xu. The Chinese . University . of Hong . Kong. University of Science and Technology of China. . 1. SSD Storage. Memory and Performance. Many . of the following slides are taken with permission from . Complete . Powerpoint. Lecture Notes for. Computer Systems: A Programmer's Perspective (CS:APP). Randal E. Bryant. T. Rogers, M O’Conner, and T. . Aamodt. MICRO 2012. Goal. Understand the relationship between schedulers (warp/wavefront) and locality behaviors . Distinguish between inter-wavefront and intra-wavefront locality. Cache. $$$$$. Memory Systems. How can we supply the CPU with enough data to keep it busy?. We will focus on . memory. issues, . which are frequently bottlenecks that limit the performance of a system.. T. Rogers, M O’Conner, and T. . Aamodt. MICRO 2012. Goal. Understand the relationship between schedulers (warp/wavefront) and locality behaviors . Distinguish between inter-wavefront and intra-wavefront locality. Computer Architecture . Winter 2015. Lecture . 3.1. : Memory Hierarchy:. What and Why?. Marc Moreno . Maza. www.csd.uwo.ca/Courses/CS3350b . [Adapted from lectures on . Computer Organization and Design. Levels of Transformation:. Good Old Moore’s Law: (Technology vs Architects). For every 18-24 months, 2x transistors on the same chip area.. Processor Speed Doubles every 18-24 months. Energy Operation halves every 18-24 months. Storage technologies and trends. Locality of reference. Caching in the memory hierarchy. CS 105. Tour of the Black Holes of Computing. Random-Access Memory (RAM). Key features. RAM. is traditionally packaged as a chip.. March 28, 2017. Agenda. Review from last lecture. Cache access. Associativity. Replacement. Cache Performance. Cache Abstraction and Metrics. Cache hit rate = (# hits) / (# hits # misses) = (# hits) / (# accesses). Goes around to every warp . and issue if ready (R). If warp is not ready (W), . skip and issue next ready warp. Issue: Warps all run at the same speed,. potentially all reaching memory access. phase together and stalling..