Additional information can be found in GBT https espacecernchGBTProjectGBTXManualsFormsAllItemsaspx lpGBT https espacecernchGBTProjectLpGBTSpecificationsLpGbtxSpecificationspdf ID: 1046125
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1. GBT and lpGBT OverviewPaulo Moreira 2018/06/18Additional information can be found in:GBT: https://espace.cern.ch/GBT-Project/GBTX/Manuals/Forms/AllItems.aspxlpGBT: https://espace.cern.ch/GBT-Project/LpGBT/Specifications/LpGbtxSpecifications.pdfhttp://cern.ch/proj-gbt2017/07/12 - Update 161
2. HEP Optical Link ArchitectureWG6: High Speed Links1st Workshop: High Speed Links2On-DetectorRadiation Hard ElectronicsOff-DetectorCommercial Off-The-Shelf (COTS)SerDesTIALDPDLDCustom ASICsTiming & TriggerDAQSlow ControlTiming & TriggerDAQSlow ControlFPGANo or small radiation dosesHigh radiation dosesLHC: up to 100 Mrad (1014 1MeV n/cm2)HL – LHC: up to 1 Grad (1016 1MeV n/cm2)Short distance optical links: 50 to 300 mElectrical links to the frontendmodules. Lengths: cm to few m Custom optocomponents
3. http://cern.ch/proj-gbt2017/07/12 - Update 163GBTX
4. The GBT Systemhttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch4FEModuleFEModulePhase – Aligners + Ser/Des for E – PortsFEModuleE – PortE – PortE – PortGBT – SCAE – PortPhase - ShifterE – PortE – PortE – PortE – PortCDRDEC/DSCRSERSCR/ENCI2C MasterI2C SlaveControl LogicConfiguration(e-Fuses + reg-Bank)Clock[7:0]CLK ManagerCLK Reference/xPLLExternal clock referencecontroldataOne 80 Mb/s portI2CPortI2C (light)JTAGJTAGPort80, 160 and 320 Mb/s portsGBTIAGBLDGBTXe-Linkclockdata-updata-downePLLTxePLLRxclocks
5. GBTX Data BandwidthThe GBTX supports three frame types:“GBT” Frame“Wide Bus” Frame“8B/10B” Frame“GBT” ModeUser bandwidth: 3.28 Gb/sUp/down-links“Wide Bus” and “8B/10B”frames are only supported for the uplinkThe downlink always uses the “GBT” frame.“8B/10B” ModeDownlink data 8B/10B encodedNo FECUser bandwidth: 3.52 Gb/s“Wide Bus” Mode:Uplink data scrambledNo FECUser bandwidth: 4.48 Gb/shttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch5GBT Frame:Frame Synchronization:DC balanced and “redundant” headerForward Error Correction:Interleaved Reed-Solomon double error correction4-bit symbols (RS(15,11))Interleaving: 2Error correction capability:2 Interleaving × 2 RS = 4 symbols = 16-bitsCode efficiency: 88/120 = 73%
6. GBTX Functionality (1/4)e-Links40 bi-directional e-LinksUp to 40 @ 80 Mb/sUp to 20 @ 160 Mb/sUp to 10 @ 320 Mb/se-Port data rate can be set independently for:each groupInput / output ports1 bi-directional e-Link:80 Mb/s40 e-Link clocks (fixed phase) programable in frequency:40/80/160/320 MHz (per group)(independently of the bit rate)Automatic, semi-automatic or user controlled phase alignment of the incoming serial data embedded in the e-PortsAutomatic alignmentTracks temperature and voltage variationsTransparent to the userWorks on any type of data:DC balanced / un-balancedA few “occasional” transition enough to ensure correct operationhttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch6Phase – Aligners + Ser/Des for E – PortsPhase - ShifterE – PortE – PortE – PortE – PortCDRDEC/DSCRSERSCR/ENCI2C MasterI2C SlaveControl LogicConfiguration(e-Fuses + reg-Bank)CLK ManagerCLK Reference/xPLLJTAGGBTXePLLTxePLLRx
7. GBTX Functionality (2/4)e-Links Special cases8B/10B mode:44 input (max @ 80 Mb/s) 36 output (max @ 80 Mb/s)(Four outputs reused as inputs)Wide-Bus mode:56 input (max @ 80 Mb/s)24 output (max @ 80 Mb/s)(16 “outputs” reused as inputs)e-Links electrical characteristicsDrivers:SLVS signalingReceivers:SLVS/LVDS signalinghttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch7Phase – Aligners + Ser/Des for E – PortsPhase - ShifterE – PortE – PortE – PortE – PortCDRDEC/DSCRSERSCR/ENCI2C MasterI2C SlaveControl LogicConfiguration(e-Fuses + reg-Bank)CLK ManagerCLK Reference/xPLLJTAGGBTXePLLTxePLLRx
8. GBTX Functionality (3/4)Phase-Shifter8 independent clocksProgramable in frequency:40 / 80 / 160 / 320 MHzProgramable in phase:0 to 360◦Phase resolution: 50 ps(for all frequencies)Clock driver electrical levels:SLVSReference clock:On package crystalBuilt-in crystal oscillatorBuilt-in VCXO based PLL (xPLL)External reference can used as wellhttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch8Phase – Aligners + Ser/Des for E – PortsPhase - ShifterE – PortE – PortE – PortE – PortCDRDEC/DSCRSERSCR/ENCI2C MasterI2C SlaveControl LogicConfiguration(e-Fuses + reg-Bank)CLK ManagerCLK Reference/xPLLJTAGGBTXePLLTxePLLRx
9. GBTX Functionality (4/4)Chip Controle-Fuse register bank for burn in configurationStandalone operationReady at power upDynamic configuration and controlI2C Slave interfaceIC control channel trough the optical linkWatchdog circuit for chip operation supervision.GBLD ControlGBLD dedicated I2C master interfaceCopies configuration burned in the GBTX into the GBLDAllows to program the GBLD either through the IC channel or through the I2C slave porthttp://cern.ch/proj-gbtPaulo.Moreira@cern.ch9Phase – Aligners + Ser/Des for E – PortsPhase - ShifterE – PortE – PortE – PortE – PortCDRDEC/DSCRSERSCR/ENCI2C MasterI2C SlaveControl LogicConfiguration(e-Fuses + reg-Bank)CLK ManagerCLK Reference/xPLLJTAGGBTXePLLTxePLLRx
10. GBTX In Numbers½ million gatesApproximately:300 8-bit programable registers(all TMR)300 8-bit e-Fuse memoryClock tree (chip wide):9 clock trees (all TMR)Frequencies: 40/80/160/320 MHz7 PLLs:RX: CDR PLL + Reference PLL (2.4 GHz)Serializer PLL (4.8 GHz)Phase-Shifter PLL (1.28 GHz)xPLL (VCXO based PLL, 80 MHz)(2x) ePLL (320 MHz)17 master DLLs:9 for phase alignment of the e-links8 for clock de-skewing56 replica delay lines:For phase alignment of the e-links7 power domains:Serializer (1.5V)DESerializer (1.5V)Clock Manager (1.5V)Phase shifter (1.5V)Core digital (1.5V)I/O (1.5V)Fuses (3.3V)http://cern.ch/proj-gbtPaulo.Moreira@cern.ch1017 mm17 mmTotal height including solder balls: ~3 mm4.3 mm4.3 mm
11. GBTX – Floor Plan and Modelling10 “Macro-cells”:Serializer:Full custom“Analogue-Verilog" modellingClock Manager:Standard cellsVerilog modellingDESerializerFull custom+ “custom” digital+ standard cells“Analogue-Verilog" + Verilog modellingXPLLFull custom“Analogue-Verilog" modellingEPLL (x2)Full custom“Analogue-Verilog" modellingPhase-ShifterFull customPhase Aligners (x8)Full custom“Analogue-Verilog" modellingPrompt (x3)Full customVerilog modellingPower on resetFull customVerilog modellinge-Fuses (x300)Foundry IPVerilog modellingPaulo.Moreira@cern.ch11SERePLLPhase-AlignersPhase-AlignersPhase-AlignersI/O CellsPhase-ShifterE-FusesPROMPTxPLLPON-RSTCLK-MANDESStandard Cells:“everywhere”http://cern.ch/proj-gbt
12. http://cern.ch/proj-gbt2017/07/12 - Update 1612lpGBT
13. OutlineLpGBTX Block DiagramMain Features:Optical LinkE-LinksSlow ControlClock DistributionPower DissipationRadiation HardnessPackageLpGBT frame and eLinks bandwidth use:Down-LinkUp-Link:FEC5FEC12eLink – Transmitter / ReceiverHigh Speed Line Driverhttp://cern.ch/proj-gbt2017/07/12 - Update 1613
14. LpGBTX Block Diagramhttp://cern.ch/proj-gbt2017/07/12 - Update 16145.12 / 10.24 Gb/s2.56 Gb/srefClk40MHzcdrOut [63:0]serIn [255:0]DEC&DSCRrxData[31:0]SCR&ENCrxEc[1:0]ePortTxeLinkOut[15:0]ecOutePortRxeLinkIn[27:0]ecIn40/…/1280 MHz40 MHzSCA(Reduced set)txData[159:0]txEc[3:0]PhaseShiftereClock[27:0]LpGBTXControlSerDes40 MHz40 MHz40 / 80 / 160 / 320 / 640 /1280 MHzrxIc[1:0]txIc[1:0]40/…/1280 MHz40 MHz40/…/320 MHzcnt[x:0]psClk[3:0]I2C (x3)adcIn[7:0]pio[15:0]analogdatacontrolclockePortClk40/…/1280 MHzecClock
15. Main Features (1/…)“Optical” link:Down-link:2.56 Gb/s (64 – bit frame)Encoding: FEC12Bandwidth:IC (Internal Control (ASIC control)): 80 Mb/sEC (External Control (SCA e-Link)): 80 Mb/sD (Data): 1.28 Gb/sEye ScanBER Monitoring based on the FEC activityhttp://cern.ch/proj-gbt2017/07/12 - Update 1615
16. Main Features (2/…)Up-link:Bandwidth @ 5.12 Gb/s (128 – bit frame):IC: 80 Mb/sEC: 80 Mb/sD:FEC12: 3.84 Gb/sFEC5: 4.48 Gb/s10.24 Gb/s (256 – bit frame)IC: 80 Mb/sEC: 80 Mb/sD:FEC12: 7.68 Gb/sFEC5: 8.96 Gb/sProgramable pre-emphasishttp://cern.ch/proj-gbt2017/07/12 - Update 1616
17. Main Features (3/…)E-Links:Down-link:Bandwidths: 80/160/320 Mb/sNumber of links*: 16/8/4“Mirror” function:80 Mb/s: no;160 Mb/s: each channel is available on 2 outputs;320 Mb/s: each channel is available on 4 outputs.One EC channel @ 80 Mbit/sUp-Link:FEC5 @ 5.12 Gb/s:Data rate: 160 / 320 / 640 Mb/s# eLinks*: 28 / 14 / 7FEC5 @ 10.24 Gb/s: Bandwidth: 320 / 640 / 1280 Mb/s# eLinks*: 28 / 14 / 7FEC12 @ 5.12 Gb/s: Bandwidth: 160 / 320 / 640 Mb/s# eLinks*: 24 / 12 / 6FEC12 @ 10.24 Gb/s: Bandwidth: 320 / 640 / 1280 Mb/s# eLinks*: 24 / 12 / 6One EC channel @ 80 Mbit/sPhase alignment on a per channel basis:User programable phaseAutomatic phase trackinghttp://cern.ch/proj-gbt2017/07/12 - Update 1617* Excluding the EC channel
18. Main Features (4/…)LatencyBoth the RX and TX will have fixed and “deterministic” latencyeLink Line DriversProgramable:Driving current: 1, 2 and 4 mACommon mode voltage: 600 mVReceiving end termination 100 WPre-emphasiseLink Line ReceiversProgramable:100 W differential terminations (on/off)Auto bias for AC coupling (on/off)Line equalizationhttp://cern.ch/proj-gbt2017/07/12 - Update 1618
19. Main Features (5/…)ASIC control:IC channel: 80 Mb/sI2C interfaceEC channel with double role:When the LpGBT works as a Transceiver:The EC channel is used to convey (control) data to and from the GBT – SCA, an ASIC or a frontend moduleWhen the LpGBT works as a Simplex Receiver or Transmitter:The EC channel is used as an ASIC control channel (having a similar role and functionality as the IC channel).http://cern.ch/proj-gbt2017/07/12 - Update 1619
20. Main Features (6/…)Slow Control:LpGLD control:I2C masterExperiment control:Two I2C mastersProgrammable parallel port:16 x DIOEnvironmental monitoring:10-bit ADC:8 inputsTemperature:On chip: yesProgramable current source to drive an external temperature sensorEnvironmental stimulus:8 – bit DAC:Single outputRange: 0 to 800 mVNoise: < 1 mVDNL: < 1 LSBINL:Full range: < 3 LSBRange 200 to 800 mV: < 1 LSBhttp://cern.ch/proj-gbt2017/07/12 - Update 1620
21. Main Features (7/…)Clock distribution:Phase/Frequency – 4 programmable clocks4 independentPhase resolution: 50 psFrequencies: 40 / 80 / 160 / 320 / 640 / 1280 MHzeLink Clocks:28 independentFixed phaseFrequency programableFrequencies: 40 / 80 / 160 / 320 / 640 / 1280 MHzClock jitter:< 5 ps rmsPower dissipation:500 mW @ 5.12 Gb/s750 mW @ 10.24 Gb/sRadiation hardness:Total dose: 200 MradSEU robusthttp://cern.ch/proj-gbt2017/07/12 - Update 1621
22. Main Features (8/.)Package:BGAFine Pitch:0.5 mmPin count:289 (17 x 17)Size:9 mm x 9 mm x 1.8 mmhttp://cern.ch/proj-gbt2017/07/12 - Update 1622
23. LpGBT Frame and eLinks Bandwidth Usehttp://cern.ch/proj-gbt2017/07/12 - Update 1623
24. DownlinkSingle data rate:2.56 Gb/sFrame:IC field:2 – bit80 Mb/sEC field:2 – bit80 Mb/sData field:32 – bit 1.28 Gb/sFEC field:24 – bitError correction:FEC:Interleaving: 4Symbol width: 3 – bitNumber of wrong symbols: 1 ( × 4)Up to 12 consecutive bitsEfficiency: 56%eLinks:Data16 eLinks @ 80 Mb/s 8 eLinks @ 160 Mb/s 4 eLinks @ 320 Mb/sEC1 eLink @ 80 Mb/shttp://cern.ch/proj-gbt2017/07/12 - Update 1624Option 37Frame (bits) 64Header (bits) 4Coded header YesUser field (bits) 36Code (bits) 248-bit multiplicity 4.5User Bandwidth (GHz)1.44# eLinks groups (8 bit)4eLinks bandwidth (MHz)80/160/320#eLinks 16/8/4EC bandwidth (MHz)80IC bandwidth (MHz)80Corrected (bits) 12Efficiency 56%
25. Uplink – FEC 5Dual data rate:5.12 Gb/s10.24 Gb/sFrame:Header:2 / 4 – bits2’b10 (high) & 2’b01 (low)IC field:2 – bit80 Mb/sEC field:2 – bit80 Mb/s Data field: 112 / 224 – bit 4.48 / 8.96 Gb/sFEC field:10 / 20 – bitError correction:FEC:Interleaving: 1 / 2Symbol width: 5 – bitNumber of wrong symbols: 1 ( × 1 / × 2) Up to 5 / 10 consecutive bitsEfficiency: 91%eLinks:Data28 eLinks @ 160 / 320 Mb/s14 eLinks @ 320 / 640 Mb/s 7 eLinks @ 640 / 1280 Mb/sEC 1 eLink @ 80 Mb/shttp://cern.ch/proj-gbt2017/07/12 - Update 1625FEC55.12 Gb/s10.24 Gb/sOption 77Frame (bits)1282 x 128Header (bits)22+2Coded headernonoUser field (bits)116232Code (bits)102016-bit multiplicity7.25014.5Remainder bits48User Bandwidth (GHz)4.649.28# eLinks groups (16 bit)77eLinks bandwidth (MHz)160/320/640320/640/1280#eLinks 28/14/728/14/7EC bandwidth (MHz)8080/160IC bandwidth (MHz)8080/160Unassigned bits04Corrected (bits)52 x 5Efficiency 91%91%
26. Uplink – FEC 12Dual data rate:5.12 Gb/s10.24 Gb/sFrame:Header:2 / 4 – bits10 (high) & 01 (low) IC field: 2 – bit80 Mb/sEC field: 2 – bit80 Mb/sData field:96 / 192 – bit 3.84 / 7.68 Gb/sFEC field:24 / 48 – bitError correction:FEC:Interleaving: 3 / 6Symbol width: 4 – bitNumber of wrong symbols: 1 ( × 3 / × 6)Up to 12 / 24 consecutive bitsEfficiency: 78% (if accounting for the unassigned bits)eLinks:Data24 eLinks @ 160 / 320 Mb/s12 eLinks @ 320 / 640 Mb/s 6 eLinks @ 640 / 1280 Mb/sEC 1 eLink @ 80 Mb/shttp://cern.ch/proj-gbt2017/07/12 - Update 1626FEC125.12 Gb/s10.24 Gb/sOption 2828Frame (bits)1282 x 128Header (bits)22+2Coded headernonoUser field (bits)102204Code (bits)244816-bit multiplicity6.37512.75Remainder bits612User Bandwidth (GHz)4.088.16# eLinks groups (16 bit)66eLinks bandwidth (MHz)160/320/640320/640/1280#eLinks 24/12/624/12/6EC bandwidth (MHz)8080/160IC bandwidth (MHz)8080/160Unassigned bits28Corrected (bits)122 x 12Efficiency 80%80%
27. eLink – Transmitter / Receiver OverviewSignaling: “CERN Low Power Signaling” (CLPS)Down-link Transmitter (eTx):Bandwidths:Data: up to 320 Mb/sTo be used as a macro cell the eTx will be designed to support 1.28 Gb/s data transmissionClock: up to 1.28 GHzProgramable:Driving current: 1 to 4 mA in 0.5 mA stepsReceiving end termination 100 WVoltage amplitude in 100 W:100 mV to 400 mV (single-ended PP amplitude)200 mV to 800 mV (differential PP amplitude)Common mode voltage: 600 mVPre-emphasis:Driving current: 1 to 4 mA in 0.5 mA stepsPulse width: T bit / 2Up-Link Receiver (eRx):Bandwidth:Data: up to 1.28 Gb/sProgramable:100 W differential terminations (on/off)Auto bias for AC coupling (on/off)Line equalizationUnder specificationhttp://cern.ch/proj-gbt2017/07/12 - Update 1627Vout+Vout-Single-ended PP amplitude:max(Vout+) – min(Vout+)Differential PP amplitude:max(Vout+ - Vout-) – min(Vout+ - Vout-)Vcm:
28. ParameterDescriptionMinNomMaxUnitsVDDSupply voltage range1.081.21.32VIDDAverage current consumption 850 μAVCMRXCommon-mode voltage rangeA706001200mVVCMCommon-mode set voltageB VDD/2 |VID|Differential voltageC140200450EmVVIDTHDifferential inputC high threshold 70mVVIDTLDifferential inputC low threshold-70 mVVIHSingle-ended input high voltage 700VDD+200mVVILSingle-ended input low voltage-40500 mVZIDDifferential input impedance80100125ΩJRRandom noise jitter 10Fps rmsJPWPattern or pulse width dependent jitterD 10FpsTR/FOutput rise/fall time 30 psPSRPower supply rejection 10Fps/100mVCMRCommon mode rejection 10Fps/100mVCCMCommon mode termination capacitance tbd. pFLOOutput load 100 fFeRx Specificationhttp://cern.ch/proj-gbt2017/07/12 - Update 1628A Common mode: (VDP + VDN) / 2B For AC coupled signalsC Differential voltage: VDP - VDND Change of delay through the receiver with PRBS 212-1 @ 1.28Gbit/s or varying pulse width TPW > 1nsE For LVDS: 400mVF If <=1ps possible (even with reduced input range), receiver could be used as hit receiver
29. eTx Specificationhttp://cern.ch/proj-gbt2017/07/12 - Update 1629ParameterDescriptionMinNomMaxUnitsVDDSupply voltage range1.081.21.32VVCMTXCommon-mode voltageA,B430600770mV|ΔVCMTX(1,0)|VCMTX mismatch when output is Differential-1 or Differential-0 5mV|VOD|Differential voltageB,C140200270mV|ΔVOD|VOD mismatch when output is Differential-1 or Differential-0 10mVVOHSingle-ended output high voltageB 700900mVVOLSingle-ended output low voltageB300500 mVIMODModulation output current D0.7 1 to 45.4 mAIPREPre-emphasis output current D0.71 to 45.4mAZLLoad impedance 100 ΩA Common mode: (VDP + VDN) / 2.B Value when driving into differential load impedance 100 Ω. Termination load is external.C Differential voltage: VDP - VDN ,values for 2mA setting, scales accordingly for other currents.D Modulation and pre-emphasis currents are programable in 0.5 mA steps from 1 mA to 4 mA. Default setting for the LpGBT is 2mA.
30. 5 - 10 Gb/s Line Driver Specificationshttp://cern.ch/proj-gbt2017/07/12 - Update 1630#SpecificationMinTypMaxUnitNotes1.1Supply Voltage 1.2 V 1.2Supply Current 40 mA 1.3Input Swing0.2 0.8VDifferential1.4Output Swing0.2 0.6VDifferential, programmable1.5Emphasis Magnitude0 10dBProgrammable1.6Rise/Fall Time 40ps 1.7Random Jitter 1.2ps 1.8Deterministic Jitter 20ps 1.9Input Common Voltage 0.75 V 1.10Input Capacitance300fF