SNALS SNALS BIT UNIVERSAL SHIFTSTORAGE REGISTERS WITH STATE OUTPUTS SDASB DECEMBER - PDF document

8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS SDAS220B ± DECEMBER 1982 ± REVISED DECEMBER 1994 1994, Texas Instruments Incorporated POST OFFICE BOX 655303 DALLAS, TEXAS 75265Operate With Outputs Enabled or at HighCan Be Cascaded for n-Bit Word Lengths , OE2 the modes of operation listed in the function table.Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputsin the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Readingout of the register can be accomplished while the outputs are enabled in any mode. Clearing occursasynchronously when the clear (CLR ) input is low. Taking either OE1 or OE2 high disables the outputs, but hasno effect on clearing, shifting, or storing data.The SN54ALS299 is characterized for operation over the full military temperature range of ±55SN74ALS299 is characterized for operation from 0 12356781020191816151413OE1 OE2 G/QGE/QEC/QCA/QAQA4CLR ...J P...DW OR N PACKAGE(TOP VIEW) 3212019910111213 OE2OE1S0CLKB/QS1CLRGNDSRVCC ...FK PACKAGE(TOP VIEW) B PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters. 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERSWITH 3-STATE OUTPUTS 2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265FUNCTION TABLE MODE INPUTS I/O PORTS OUTPUTS MODE CLR S1 S0 OE1 ² OE2 ² CLK SL SR A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH QA4 QH4 Clear LLL XLH LXH LLX LLX XXX XXX XXX LLX LLX LLX LLX LLX LLX LLX LLX LLL LLL Hold HH LX LX L L XL X X QQA0 QB0QB0 QQC0 QD0QD0 QQE0 QQF0 QQG0 QQH0 QQA0 QQH0 Right H L H L L = X HL HL QQAn QBnQBn QQCn QDnQDn QQEn QQFn QQGn HL QGnQGn Left H H L L L = HL X QQBn QQCn QDnQDn QQEn QQFn QQGn QQHn HL QQBn HL H H H X X = X X a b c d e f g h a h NOTE:a...h = the level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flipare isolated from the I/O terminals.When one or both output-enable inputs are high, the eight I/O terminals are disabled to the high-impedance state; however, sequor clearing of the register is not affected.logic symbol SRG8 M 3 R9 14 5 15 4 8 2 3 01S0 119S1 12CLK 5, 13 1,4D 3,4D7 6, 13 3,4D13 12, 13 2,4D18SL 3,4D16 &3 EN13C4/1"/2uQA4QH4CLR OE1 OE2 A/Q Z5 Z12 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS SDAS220B ± DECEMBER 1982 ± REVISED DECEMBER 1994 3 POST OFFICE BOX 655303 DALLAS, TEXAS 75265logic diagram (positive logic) C11D C11D (shift right OE2 716A/QH/Q 9 1 (14), E/Q (15), and G/Q (4).absolute maximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage, V . . . . . . . . :All inputs . . . . :SN54ALS299 ±55SN74ALS299 0Storage temperature range ±65Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditiimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERSWITH 3-STATE OUTPUTS 4 POST OFFICE BOX 655303 DALLAS, TEXAS 75265recommended operating conditions SN54ALS299 SN74ALS299 UNIT MIN NOM MAX MIN NOM MAX UNIT V Supply voltage 4.5 5 5.5 4.5 5 5.5 V V High-level input voltage 2 2 V V Low-level input voltage 0.7 0.8 V I Highlevelout p utcurrent QA4 or QH4 ±0.4 ±0.4 mA I - v o u u t c u QAH ±2.6 mA I Lowlevelout p utcurrent QA4H4 4 8 I le v el o u tp u t c u rrent QAH 24 mA TA Operating free-air temperature ±55 0 70 5C electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted) PARAMETER TESTCONDITIONS SN54ALS299 SN74ALS299 UNIT PARAMETER TEST CONDITIONS MIN TYP² MAX MIN TYP² MAX UNIT V = 4.5 V, = ±18 mA ±1.5 ±1.5 V All outputs = 4.5 V to 5.5 V, = ±0.4 mA ±2 ±2 V QAQH =45V = ±1 mA 3.3 V Q A ± Q H V = 4 . 5 V = ±2.6 mA 3.2 orQ =45V I 0.4 0.25 0.4 V Q A4 or Q H4 V = 4 . 5 V I = 8 mA 0.5 V V QAQH =45V = 12 mA 0.25 0.4 0.25 0.4 V Q A ± Q H V = 4 . 5 V = 24 mA 0.35 0.5 II A ± H =55V = 5.5 V 0.1 0.1 mA I I Any others V = 5 . 5 V VI = 7 V 0.1 mA I³ = 5.5 V, = 2.7 V 20 20 mA I³ S0, S1, SR, SL =55V =04V ±0.2 ±0.2 mA I ³ Any others V = 5 . 5 V , V = 0 . 4 V ±0.1 ±0.1 mA I§ QA4 or QH4 =55V =225V ±15 ±15 mA I O § QAH V = 5 . 5 V , V = 2 . 25 V ±20 ±112 ±30 ±112 mA Outputs high 15 28 15 28 I = 5.5 V Outputs low 22 38 22 38 mA Outputs disabled 23 40 23 40 = 5 V, T = 25 and I include the off-state output current. current, I 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS SDAS220B ± DECEMBER 1982 ± REVISED DECEMBER 1994 5 POST OFFICE BOX 655303 DALLAS, TEXAS 75265timing requirements over recommended ranges of supply voltage and operating free-airtemperature (unless otherwise noted) SN54ALS299 SN74ALS299 UNIT MIN MAX MIN MAX UNIT clock Clock frequency (at 50% duty cycle) 0 17 0 30 MHz t Pulseduration CLK high or low 22 16.5 ns t w P u lse d u ration CLR low 12 10 ns = S0 or S1 25 20 t Setup time before CLK = Serialorparalleldata High 18 16 ns t S i a l or para ll e l d a t a Low 15 6 ns Inactive-state setup time before CLK=² CLR 15 15 th HoldtimeafterCLK S0 or S1 0 0 ns t h H o ld ti me a ft er CLK= Serial or parallel data 0 0 ns switching characteristics (see Figure 1)PARAMETER FROM(INPUT) = 4.5 V to 5.5 V, = 50 pF, UNIT SN54ALS299 SN74ALS299 MIN MAX MIN MAX f 30 MHz t 2 4 13 ns tPHL CLK Q A± Q H 4 25 7 19 ns t orQ 2 5 15 ns tPHL CLK Q A4 or Q H4 4 8 18 ns tPHL CLR QAH 6 6 22 ns t PHL CLR QA4H4 6 6 22 ns t OE2 5 6 16 ns t OE2 Q A± Q H 6 27 8 22 ns t S0S1 5 7 17 ns t S1 Q A± Q H 6 26 8 22 ns tPHZ OE1 OE2 1 15 1 8 ns t OE2 Q A± Q H 4 38 5 15 ns tPHZ S0S1 QAQH 1 16 1 12 ns t S1 Q A± Q H 4 34 8 25 ns ³For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERSWITH 3-STATE OUTPUTS 6 POST OFFICE BOX 655303 DALLAS, TEXAS 75265PARAMETER MEASUREMENT INFORMATIONSERIES 54ALS/74ALS AND 54AS/74AS DEVICES 0.3 VFOR 3-STATE OUTPUTSUnder Test Test VOLTAGE WAVEFORMSTiming 1.3 V1.3 V VOLTAGE WAVEFORMSPULSE DURATIONS 1.3 V1.3 V1.3 V1.3 VWaveform 1Waveform 21.3 V1.3 V VOLTAGE WAVEFORMSPROPAGATION DELAY TIMESVOLTAGE WAVEFORMSENABLE AND DISABLE TIMES, 3-STATE OUTPUTS Test Under TestFOR OPEN-COLLECTOR OUTPUTS BI-STATETOTEM-POLE OUTPUTSUnder Test Test RL RL = R1 = R2 NOTES:A.C includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.When measuring propagation delay items of 3-state outputs, switch S1 is open.D.All input pulses have the following characteristics: PRR E.The outputs are measured one at a time with one transition per measurement.Figure 1. Load Circuits and Voltage Waveforms PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status(1) Package Type PackageDrawing Pins PackageQty Eco Plan(2) Lead finish/Ball material(6) MSL Peak Temp(3) Op Temp (°C) Device Marking(4/5) Samples 83021012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 83021012ASNJ54ALS299FK 8302101RA ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 8302101RASNJ54ALS299J 8302101SA ACTIVE CFP W 20 1 TBD SNPB N / A for Pkg Type -55 to 125 8302101SASNJ54ALS299W SN74ALS299DW ACTIVE SOIC DW 20 25 Green (RoHS& no Sb/Br) NIPDAU Level-1-260C-UNLIM 0 to 70 ALS299 SN74ALS299N ACTIVE PDIP N 20 20 Pb-Free(RoHS) NIPDAU N / A for Pkg Type 0 to 70 SN74ALS299N SNJ54ALS299FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 83021012ASNJ54ALS299FK SNJ54ALS299J ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 8302101RASNJ54ALS299J SNJ54ALS299W ACTIVE CFP W 20 1 TBD SNPB N / A for Pkg Type -55 to 125 8302101SASNJ54ALS299W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of threshold. Antimony trioxide basedflame retardants must also meet the threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2020 Addendum-Page 2 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ALS299, SN74ALS299 :•Catalog: SN74ALS299•Military: SN54ALS299 NOTE: Qualified Version Definitions:•Catalog - TI's standard catalog product•Military - QML certified for Military and Defense Applications www.ti.comPACKAGE OUTLINE C TYP10.639.97 2.65 MAX 18X 1.27 20X 0.51 2X11.43 TYP0.33 0 - 8 0.3 0.25GAGE PLANE 1.27 ANOTE 313.0 B7.6 4220724/A 05/2016SOIC - 2.65 mm max heightDW0020ASOICNOTES: 120 0.25 CAB1110 PIN 1 IDAREANOTE 4 SEATING PLANE 0.1C SEE DETAIL ADETAIL ATYPICALSCALE 1.200 www.ti.comEXAMPLE BOARD LAYOUT(9.3) 0.07 MAXALL AROUND 0.07 MIN 20X (2) 20X (0.6) 18X (1.27) (R)TYP0.05 4220724/A 05/2016SOIC - 2.65 mm max heightDW0020ASOICSYMM SYMM LAND PATTERN EXAMPLESCALE:6X1101120NOTES: (continued) METAL SOLDER MASKNON SOLDER MASKDEFINEDSOLDER MASK DETAILS SOLDER MASK METAL UNDERSOLDER MASKDEFINED www.ti.comEXAMPLE STENCIL DESIGN(9.3) 18X (1.27) 20X (0.6) 20X (2) 4220724/A 05/2016SOIC - 2.65 mm max heightDW0020ASOICNOTES: (continued) SYMM SYMM 1101120SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCILSCALE:6X IMPORTANTNOTICEANDDISCLAIMER “ASIS”