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Victor P. Nelson Computer-Aided Design of ASICs Victor P. Nelson Computer-Aided Design of ASICs

Victor P. Nelson Computer-Aided Design of ASICs - PowerPoint Presentation

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Victor P. Nelson Computer-Aided Design of ASICs - PPT Presentation

Victor P Nelson ComputerAided Design of ASICs Concept to Silicon ASIC Design Flow Behavioral Model VHDLVerilog GateLevel Netlist TransistorLevel Netlist Physical Layout MapPlaceRoute DFTBIST ID: 772190

count4 design amp adk design count4 adk amp exmplr file netlist load test logic scan port std verilog clock

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Victor P. Nelson Computer-Aided Design of ASICs Concept to Silicon

ASIC Design Flow Behavioral Model VHDL/Verilog Gate-LevelNetlist Transistor-LevelNetlist PhysicalLayoutMap/Place/Route DFT/BIST & ATPG Verify Function Verify Function Verify Function & Timing Verify Timing DRC & LVS Verification IC Mask Data/FPGA Configuration File Standard Cell IC & FPGA/CPLD Synthesis Test vectors Full-custom IC Front-End Design Back-End Design

ASIC CAD tools available in ECE Modeling and Simulation Modelsim , ADVance MS/Questa, Eldo , Mach TA/ADiT (Mentor Graphics)Verilog-XL, NC_Verilog , Spectre (Cadence)Design Synthesis (digital)Leonardo Spectrum, Precision RTL (Mentor Graphics)Design Compiler (Synopsys), RTL Compiler (Cadence) Design for Test and Automatic Test Pattern GenerationDFT Advisor, Fastscan, Flextest (Mentor Graphics)Schematic Capture & Design Integration Design Architect-IC (Mentor Graphics)Design Framework II (DFII) - Composer (Cadence)Physical Layout IC Station (Mentor Graphics)SOC Encounter, Virtuoso (Cadence)Design VerificationCalibre (Mentor Graphics)Diva, Assura (Cadence)

Mentor Graphics Analog/Mixed-Signal IC Design Flow

Mentor Graphics CAD Tools (select from “ eda ” list in user-setup on the Sun network)ICFlow** – For custom & standard cell IC designs IC flow tools (Design Architect-IC, IC Station, Calibre) Digital/analog/mixed simulation (Modelsim,ADVance MS,Eldo,MachTA )HDL Synthesis (Leonardo)ASIC Design Kit (ADK)** Support files for various technologies DFTATPG/DFT/BIST tools (DFT Advisor, Flextest, Fastscan )Modelsim** (HDL Simulation) FPGA (FPGA Advantage, Modelsim, Leonardo)*Xilinx/ISE (Xilinx FPGA/CPLD - back end design)* QuartusII (Altera FPGA/CPLD - back end design)*Ims /6.2 (IMS chip tester) ** Installed on both Solaris and Linux servers * Vendor-Provided (Not Mentor Graphics) Tools

Mentor Graphics ASIC Design Kit (ADK) Technology files & standard cell libraries AMI: ami12, ami05 (1.2, 0.5 μm)TSMC: tsmc035, tsmc025, tsmc018 (0.35, 0.25, 0.18 μ m) IC flow & DFT tool support files:Simulation VHDL/Verilog /Mixed-Signal models (Modelsim SE/ADVance MS) Analog (SPICE) models (Eldo /Accusim) Post-layout timing (Mach TA) Digital schematic (Quicksim II, Quicksim Pro) (except tsmc025,tsmc018)Synthesis to standard cells (LeonardoSpectrum)Design for test & ATPG (DFT Advisor, Flextest/ Fastscan) Schematic capture (Design Architect-IC)IC physical design (standard cell & custom) Floorplan, place & route (IC Station) Design rule check, layout vs schematic, parameter extraction ( Calibre) We also have ADK’s for Cadence tools for several technologies

Xilinx/Altera FPGA/CPLD Design Tools Simulate designs in Modelsim Behavioral models (VHDL,Verilog)Synthesized netlists (VHDL, Verilog)Requires “primitives” library for the target technologySynthesize netlist from behavioral modelLeonardo (Levels 1,2,3) has libraries for most FPGAs (ASIC-only version currently installed)Xilinx ISE has its own synthesis toolVendor tools for back-end design Map, place, route, configure device, timing analysis, generate timing modelsXilinx Integrated Software Environment (ISE)Altera Quartus II & Max+Plus2Higher level tools for system design & managementMentor Graphics FPGA AdvantageXilinx Platform Studio : SoC design, IP management, HW/SW codesign

Behavioral Design & Verification Create Behavioral/RTL HDL Model(s) Simulate to Verify Functionality Synthesize Circuit Synopsys - Design CompilerLeonardo Spectrum,Xilinx ISE (digital) Modelsim (digital) VHDL-AMSVerilog-A ADVance MS (analog/mixed signal) VHDLVerilogSystemC Technology Libraries Technology-Specific Netlist to Back-End Tools Simulate to Verify Function/Timing VITAL Library Design Constraints

ADVance MS Digital, Analog, Mixed-Signal Simulation ADVance MS Working Library Design_1Design_2 VITAL IEEE 1164 Resource Libraries Simulation Setup EZwave or Xelga Input Stimuli VHDL,Verilog, VHDL-AMS, Verilog-A, SPICE Netlists Eldo, Eldo RF Modelsim View Results Mach TA Mach PA Analog (SPICE) Digital (VHDL,Verilog) Mixed Signal(VHDL-AMS, Verilog-A) SPICE models Xilinx SIMPRIMS

ADVance MS : mixed-signal simulation A/D converter digital analog VHDL-AMS

ADVance MS: mixed Verilog -SPICE SPICE subcircuit Verilog top(test bench)

Questa ADMS (replaces ADVance MS) Four simulation engines integrated for SoC designs Questa – VHDL/Verilog/SystemC digital simulationEldo – analog (SPICE) simulationADiT – accelerated transistor-level (Fast-SPICE) simulation (replaces Mach TA)Eldo RFEngines and languages can be mixed in a simulationIEEE 1497 Standard Delay File Format (SDF)IEEE 1076.1 VHDL-AMSIEEE 1076 VHDL IEEE 1364 VerilogIEEE 1800 SystemVerilogIEEE 1666 SystemCAccellera standard Verilog-AMS Language SPICE Eldo, HSPICE, and Spectre dialects.

Questa ADMS

Example: 4-bit binary counter VHDL model (count4.vhd)Create working library: vlib work vmap work workCompile: vcom count4.vhdSimulate: vsim count4(rtl) ModelSim simulation-control inputsModelSim “Macro” (count4_rtl.do)OR, VHDL testbench ModelSim resultslisting or waveform

-- count4.vhd 4-bit parallel-load synchronous counter LIBRARY ieee ;USE ieee.std_logic_1164.all; USE ieee.numeric_std.all ; --synthesis librariesENTITY count4 IS PORT (clock,clear,enable,load_count : IN STD_LOGIC; D: IN unsigned(3 downto 0); Q: OUT unsigned(3 downto 0));END count4; ARCHITECTURE rtl OF count4 IS SIGNAL int : unsigned(3 downto 0); BEGIN PROCESS(clear, clock, enable) BEGIN IF (clear = '1') THEN int <= "0000"; ELSIF (clock'EVENT AND clock='1') THEN IF (enable = '1') THEN IF ( load_count = '1') THEN int <= D; ELSE int <= int + "01"; END IF; END IF; END IF; END PROCESS; Q <= int ;END rtl;

Test stimulus: Modelsim “do” file: count4_rtl.do add wave /clock /clear /enable /load_count /D /Q add list /clock /clear /enable /load_count /D /Q force /clock 0 0, 1 10 -repeat 20force /clear 0 0, 1 5, 0 10force /enable 0 0, 1 25 force /load_count 0 0, 1 20, 0 35, 1 330, 0 350force /D 10#5 0, 10#9 300run 400

Testbench: count4_bench.vhd LIBRARY ieee ; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY count4_bench is end count4_bench;ARCHITECTURE test of count4_bench is component count4 PORT (clock,clear,enable,load_count : IN STD_LOGIC; D: IN unsigned(3 downto 0); Q: OUT unsigned(3 downto 0)); end component; for all: count4 use entity work.count4(behavior); signal clk : STD_LOGIC := '0'; signal clr, en, ld: STD_LOGIC; signal din, qout: unsigned(3 downto 0);begin UUT: count4 port map(clk,clr,en,ld,din,qout ); clk <= not clk after 10 ns; P1: process begin din <= "0101"; clr <= '1'; en <= '1'; ld <= '1'; wait for 10 ns; clr <= '0'; wait for 20 ns; ld <= '0'; wait for 200 ns; end process;end; Alternative to “do” file Could also check results & “assert” error messages

Count4 – Simulation waveform Parallel Load Counting Clear

Automated Synthesis with Leonardo Spectrum Leonardo Spectrum (Level 3) VHDL/Verilog Behavioral/RTL Models FPGA ASIC Technology Synthesis Libraries Technology- Specific Netlist Design Constraints VHDL, Verilog, SDF, EDIF, XNF Level 1 – FPGA Level 2 – FPGA + Timing Level 3 – ASIC + FPGA (we have Level 3 ASIC only) ADK AMI 0.5, 1.2 TSMC 0.35, 0.25

Automated Synthesis with Synopsys Design CompilerDesign Compiler (shell) Design Vision (GUI) VHDL/Verilog Behavioral/RTL Models ASIC DW Technology Synthesis Libraries Technology- Specific Netlist Design Constraints Verilog , SDF , DDC database, SDC constraints, REP report Synopsys DesignWare Component Library

Leonardo – ASIC Synthesis Flow Read & check HDL Synthesize generic gates& modules Map to technologycells & optimize Write netlist,SDF, reports

Leonardo synthesis procedure Invoke leonardo Select & load a technology library (ASIC or FPGA)ASIC > ADK > TSMC 0.35 micronRead input VHDL/ Verilog file(s): count4.vhdEnter design constraints (clock freq, delays, etc.) Optimize for area/delays/effort levelWrite output file(s)count4_0.vhd - VHDL netlist count4.v - Verilog netlist (for IC layout)count4.sdf - Standard delay format file (for timing) count4.edf - EDIF netlist (for Xilinx/Altera FPGA)

Leonardo-synthesized netlist count4_0.vhd library IEEE; use IEEE.STD_LOGIC_1164.all; library adk; use adk.adk_components.all; -- ADDED BY VPN entity count4 is port ( clock : IN std_logic ; clear : IN std_logic ; enable : IN std_logic ; load_count : IN std_logic ; D : IN std_logic_vector (3 DOWNTO 0) ; Q : OUT std_logic_vector (3 DOWNTO 0)) ; end count4 ;architecture netlist of count4 is -- rtl changed to netlist by VPN signal Q_3_EXMPLR, Q_2_EXMPLR, Q_1_EXMPLR, Q_0_EXMPLR, nx8, nx14, nx22, nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181, nx183, nx185, nx187, nx189: std_logic ; begin Q(3) <= Q_3_EXMPLR ; Q(2) <= Q_2_EXMPLR ; Q(1) <= Q_1_EXMPLR ; Q(0) <= Q_0_EXMPLR ; Q_0_EXMPLR_EXMPLR : dffr port map ( Q=>Q_0_EXMPLR, QB=>OPEN, D=>nx126, CLK=>clock, R=>clear); ix127 : mux21_ni port map ( Y=>nx126, A0=>Q_0_EXMPLR, A1=>nx8, S0=>enable ); ix9 : oai21 port map ( Y=>nx8, A0=>load_count, A1=>Q_0_EXMPLR, B0=>nx169 ); ix170 : nand02 port map ( Y=>nx169, A0=>D(0), A1=>load_count ); Q_1_EXMPLR_EXMPLR : dffr port map ( Q=>Q_1_EXMPLR, QB=>OPEN, D=>nx136, CLK=>clock, R=>clear); ix137 : mux21_ni port map ( Y=>nx136, A0=>Q_1_EXMPLR, A1=>nx28, S0=> enable); ix29 : ao22 port map ( Y=>nx28, A0=>D(1), A1=>load_count, B0=>nx14, B1=> nx22); ix15 : or02 port map ( Y=>nx14, A0=>Q_0_EXMPLR, A1=>Q_1_EXMPLR); ix23 : aoi21 port map ( Y=>nx22, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, B0=> load_count); Q_2_EXMPLR_EXMPLR : dffr port map ( Q=>Q_2_EXMPLR, QB=>OPEN, D=>nx146, CLK=>clock, R=>clear); ix147 : mux21_ni port map ( Y=>nx146, A0=>Q_2_EXMPLR, A1=>nx48, S0=> enable); ix49 : oai21 port map ( Y=>nx48, A0=>nx181, A1=>nx183, B0=>nx189); ix182 : aoi21 port map ( Y=>nx181, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, B0=> Q_2_EXMPLR); ix184 : nand02 port map ( Y=>nx183, A0=>nx185, A1=>nx187); ix186 : inv01 port map ( Y=>nx185, A=>load_count); ix188 : nand03 port map ( Y=>nx187, A0=>Q_2_EXMPLR, A1=>Q_1_EXMPLR, A2=> Q_0_EXMPLR); ix190 : nand02 port map ( Y=>nx189, A0=>D(2), A1=>load_count); Q_3_EXMPLR_EXMPLR : dffr port map ( Q=>Q_3_EXMPLR, QB=>OPEN, D=>nx156, CLK=>clock, R=>clear); ix157 : mux21_ni port map ( Y=>nx156, A0=>Q_3_EXMPLR, A1=>nx62, S0=> enable); ix63 : mux21_ni port map ( Y=>nx62, A0=>nx54, A1=>D(3), S0=> load_count); ix55 : xnor2 port map ( Y=>nx54, A0=>Q_3_EXMPLR, A1=>nx187);end netlist ;

// Verilog description for cell count4, LeonardoSpectrum Level 3, 2005a.82 module count4 ( clock, clear, enable, load_count, D, Q ) ; input clock ; input clear ; input enable ; input load_count ; input [3:0]D ; output [3:0]Q ; wire nx8, nx14, nx22, nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181, nx183, nx185, nx187, nx189; wire [3:0] \$dummy ; dffr Q_0__rename_rename (.Q (Q[0]), .QB (\$dummy [0]), .D (nx126), .CLK (clock), .R (clear)) ; mux21_ni ix127 (.Y (nx126), .A0 (Q[0]), .A1 (nx8), .S0 (enable)) ; oai21 ix9 (.Y (nx8), .A0 (load_count ), .A1 (Q[0]), .B0 (nx169)) ; nand02 ix170 (.Y (nx169), .A0 (D[0]), .A1 (load_count)) ; dffr Q_1__rename_rename (.Q (Q[1]), .QB (\$dummy [1]), .D (nx136), .CLK (clock), .R (clear)) ; mux21_ni ix137 (.Y (nx136), .A0 (Q[1]), .A1 (nx28), .S0 (enable)) ; ao22 ix29 (.Y (nx28), .A0 (D[1]), .A1 (load_count), .B0 (nx14), .B1 (nx22) ) ; or02 ix15 (.Y (nx14), .A0 (Q[0]), .A1 (Q[1])) ; aoi21 ix23 (.Y (nx22), .A0 (Q[1]), .A1 (Q[0]), .B0 (load_count)) ; dffr Q_2__rename_rename (.Q (Q[2]), .QB (\$dummy [2]), .D (nx146), .CLK (clock), .R (clear)) ; mux21_ni ix147 (.Y (nx146), .A0 (Q[2]), .A1 (nx48), .S0 (enable)) ; oai21 ix49 (.Y (nx48), .A0 (nx181), .A1 (nx183), .B0 (nx189)) ; aoi21 ix182 (.Y (nx181), .A0 (Q[1]), .A1 (Q[0]), .B0 (Q[2])) ; nand02 ix184 (.Y (nx183), .A0 (nx185), .A1 (nx187)) ; inv01 ix186 (.Y (nx185), .A (load_count )) ; nand03 ix188 (.Y (nx187), .A0 (Q[2]), .A1 (Q[1]), .A2 (Q[0])) ; nand02 ix190 (.Y (nx189), .A0 (D[2]), .A1 (load_count)) ; dffr Q_3__rename_rename (.Q (Q[3]), .QB (\$dummy [3]), .D (nx156), .CLK (clock), .R (clear)) ; mux21_ni ix157 (.Y (nx156), .A0 (Q[3]), .A1 (nx62), .S0 (enable)) ; mux21_ni ix63 (.Y (nx62), .A0 (nx54), .A1 (D[3]), .S0 ( load_count)) ; xnor2 ix55 (.Y (nx54), .A0 (Q[3]), .A1 (nx187)) ; endmodule

Post-synthesis simulation ( Leonardo -generated netlist)Verify synthesized netlist matches behavioral model Create library of std cell simulation primitives: >vlib adk >vcom $ADK/technology/adk.vhd >vcom $ADK/technology/adk_comp.vhdInsert library/package declaration into netlist library adk; use adk.adk_components.all; Simulate in Modelsim, using “do file” or test bench from original behavioral simulation results should match VITAL models of ADK std cells

Post-synthesis timing analysis Leonardo can generate SDF (std. delay format) file with technology-specific, VITAL-compliant timing parameters (from cell library) (CELLTYPE " dffr ") (INSTANCE Q_0_EXMPLR_EXMPLR) (DELAY (ABSOLUTE (PORT D (::0.00) (::0.00)) (PORT CLK (::0.00) (::0.00)) (PORT R (::0.00) (::0.00)) (IOPATH CLK Q (::0.40) (::0.47)) (IOPATH R Q (::0.00) (::0.55)) (IOPATH CLK QB (::0.45) (::0.36)) (IOPATH R QB (::0.53) (::0.00)))) (TIMINGCHECK (SETUP D (posedge CLK) (0.47)) (HOLD D (posedge CLK) (-0.06)))) Path delays (min:typ:max) Delays lumped at pins Constraints

VITAL Model (1) library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Primitives.all; use IEEE.VITAL_Timing.all ;entity and02 is generic ( tipd_A0 : VitalDelayType01Z := VitalZeroDelay01Z; tipd_A1 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_A0_Y : VitalDelayType01Z := VitalZeroDelay01Z; tpd_A1_Y : VitalDelayType01Z := VitalZeroDelay01Z ); port ( A0 : in STD_LOGIC; A1 : in STD_LOGIC; Y : out STD_LOGIC ); attribute VITAL_LEVEL0 of and02 : entity is TRUE;end and02; Delays fromSDF file

VITAL Model (2) architecture and02_arch of and02 is attribute VITAL_LEVEL1 of and02_arch : architecture is TRUE; signal A0_ipd : STD_LOGIC := 'X'; signal A1_ipd : STD_LOGIC := 'X';begin WireDelay : Block begin VitalWireDelay (A0_ipd, A0, tipd_A0); VitalWireDelay (A1_ipd, A1, tipd_A1); end Block; VitalBehavior : Process (A0_ipd, A1_ipd) VARIABLE INT_RES_0 : STD_LOGIC := 'X'; VARIABLE GlitchData_Y : VitalGlitchDataType; begin -- FUNCTIONALITY SECTION -- INT_RES_0 := VitalAnd2 (A0_ipd, A1_ipd); Determine inputpin delays Ideal (zero-delay) AND function

VITAL Model (3) -- PATH DELAY SECTION -- VitalPathDelay01Z ( OutSignal => Y, OutSignalName => "Y", OutTemp => INT_RES_0, Paths => ( 0 => ( InputChangeTime => A0_ipd'LAST_EVENT, PathDelay => tpd_A0_Y, PathCondition => TRUE ), 1 => ( InputChangeTime => A1_ipd'LAST_EVENT, PathDelay => tpd_A1_Y, PathCondition => TRUE ) ), GlitchData => GlitchData_Y, Mode => OnDetect, MsgOn => TRUE, Xon => TRUE, MsgSeverity => WARNING Determine delay alongeach input-output path

Design for test & test generation Consider test during the design phaseTest design more difficult after design frozenBasic steps:Design for test (DFT) – insert test points, scan chains, etc. to improve testability Insert built-in self-test (BIST) circuitsGenerate test patterns (ATPG)Determine fault coverage (Fault Simulation)

DFT & test design flow Memory & Logic BIST Boundary Scan InternalScan Design ATPG

DFTadvisor/FastScan Design Flow Source: FlexTest Manual DFT/ATPG Library:adk.atpg count4.vhd count4_0.vhd count4.v count4_scan.v Leonardo

ASIC DFT Flow Insert Internal Scan Circuitry Generate/Verify Test Vectors Synthesized VHDL/Verilog Netlist adk.atpg ATPG Library DFT Advisor Fastscan/ Flextest VHDL/ Verilog Netlist With Scan Elements Test Pattern File

Example DFTadvisor session Invoke: dftadvisor –verilog count4.v –lib $ADK/technology/adk.atpg Implement scan with defaults: (full scan, mux-DFF scan elements)set system mode setupanalyze control signals –auto set system mode dftruninsert test logic write netlist count4_scan.v –verilogwrite atpg setup count4_scan (creates count4_scan.dofile for ATPG in Fastscan)

count4 – without scan design

count4 – scan inserted by DFTadvisor

ATPG with FastScan (full-scan circuit) Invoke: fastscan – verilog count4.v –lib $ADK/technology/adk.atpgGenerate test pattern file in FastScan :dofile count4_scan.dofile (defines scan path & procedure) ** set system mode atpgcreate patterns –auto (generate test patterns)save patterns ** “count4_scan.dofile” was created by DFTadvisor

Test file: scan chain definition and load/unload procedures scan_group "grp1" = scan_chain "chain1" = scan_in = "/scan_in1"; scan_out = "/output[3]"; length = 4; end; procedure shift "grp1_load_shift" = force_sci "chain1" 0; force "/clock" 1 20; force "/clock" 0 30; period 40; end; procedure shift "grp1_unload_shift" = measure_sco "chain1" 10; force "/clock" 1 20; force "/clock" 0 30; period 40; end; procedure load "grp1_load" = force "/clear" 0 0; force "/clock" 0 0; force "/scan_en" 1 0; apply "grp1_load_shift" 4 40; end; procedure unload "grp1_unload" = force "/clear" 0 0; force "/clock" 0 0; force "/scan_en" 1 0; apply "grp1_unload_shift" 4 40; end;end;

Generated scan-based test // send a pattern through the scan chain CHAIN_TEST = pattern = 0; apply "grp1_load" 0 = (use grp1_load procedure) chain "chain1" = "0011"; (pattern to scan in) end; apply "grp1_unload" 1 = (use grp1_unload procedure) chain "chain1" = "1100"; (pattern scanned out) end;end; // one of 14 patterns for the counter circuit pattern = 0; (pattern #) apply "grp1_load" 0 = (load scan chain) chain "chain1" = "1000"; (scan-in pattern) end; force "PI" "00110" 1; (PI pattern) measure "PO" "0010" 2; (expected POs) pulse "/clock" 3; (normal op. cycle) apply "grp1_unload" 4 = (read scan chain) chain "chain1" = "0110"; (expected pattern) end;

ASIC Physical Design (Standard Cell) (can also do full custom layout) Floorplan Chip/Block Place & RouteStd. Cells Component-Level Netlist (EDDM format)IC Mask Data Design RuleCheck Std. Cell Layouts Mentor Graphics “IC Station” (adk_ic) Mach TA/Eldo Simulation Model Backannotate Schematic Generate Mask Data Layout vs. Schematic Check Design Rules Process Data Libraries Calibre Calibre Calibre ICblocks

Cell-Based IC I/O pads

Cell-Based Block

Source: Weste “CMOS VLSI Design” Basic standard Cell layout

Preparation for Layout Use Design Architect-IC to convert Verilog netlist to Mentor Graphics EDDM netlist formatInvoke Design Architect-IC (adk_daic )On menu bar, select File > Import Verilog Netlist file: count4.v (the Verilog netlist )Output directory: count4 (for the EDDM netlist )Mapping file $ADK/technology/adk_map.vmp Open the generated schematic for viewingClick Schematic in DA-IC palette Select schematic in directory named above (see next slide)Click Update LVS in the schematic palette to create a netlist to be used later by “ Calibre”Create design viewpoints for ICstation toolsadk_dve count4 –t tsmc035 (V.P’s: layout, lvs , sdl, tsmc035) Can also create gate/transistor schematics directly in DA-IC using components from the ADK library

DA-IC generated schematic

Eldo simulation from DA-IC Run simulations from within DA-IC Eldo , ADVance MS, Mach TADA-IC invokes a “netlister” to create a circuit model from the schematicSPICE model for Eldo & Mach TAEldo analyses, forces, probes, etc. same as SPICEView results in EZwave

Eldo input and output files -Netlist -Simulation cmds -Stimulus

SPICE netlist for modulo7 counter SPICE “circuit” file generated by DA-IC Force values (created interactively) From ADK library

Force functions (1) DC value V signame A 0 DC 5 Value (volts) Between circuit nodes A and GND (node 0) V indicates voltage Force name

Force functions (2) Pulse/square wave V signame B 0 pulse 0 5 0 0.1N 0.1N 20N 40N InitialVoltagev1 PulsedVoltagev2 Delay from start of period for waveform to begin - td Rise Fall time time tr tf Pulse Periodwidth tp tw v1 v2 td tr tw tf Nodes tp

Force functions (3) Pattern wave (for logic 0 & 1 values) Vname B 0 pattern 5 0 5n 0.1n 0.1n 10n 011010 RLogic 1 & 0 voltages Between circuit Nodes B & GND (node 0) Bit pattern Repeat the pattern (optional) Delay to waveform begin Rise & FallTime between changes Duration ofbit value 0 1 1 0 1 0 delay pattern

Eldo simulation of modulo7 counter (transient analysis)

Create a std-cell based logic block in IC Station Invoke: adk_ic In IC Station palette, select: Create CellCell name: count4Attach cell library: $ADK/technology/ ic/process/tsmc035Process data: $ADK/technology/ic /process/tsmc035Design rules: $ADK/technology/ic/process/tsmc035.rulesAngle mode: 45Cell type: block Select With connectivity (use imported schematic) EDDM schematic viewpoint: count4/layoutLogic loading options: flat

Create Cell dialog box

Auto-”floorplan” the block place & route > autofp

Auto-place the std cells Autoplc > StdCel

Auto-place ports ( signal connections on cell boundaries) Autoplc > Ports

AutoRoute all nets(hand-route any unrouted “overflows”) Then: Add > Port Text to copy port names from schematic – for Calibre

Layout design rule check (DRC) Technology-specific design rules specify minimum sizes, spacing, etc. of features to ensure reliable fabrication Design rules file specified at startup Ex. tsmc035.rules From main palette, select ICrules Click Check and then OK in prompt box (can optionally select a specific area to check)Rules checked in numeric order

Common errors detected by DRC To fix, click on First in palette to highlight first error Error is highlighted in the layoutClick View to zoom in to the error (see next)Example: DRC9_2: Metal2 spacing = 3LFix by drawing a rectangle of metal2 to fill in the gap between contacts that should be connected Click Next to go to next error, until all are fixed NOTE: There can be no DRC errors if MOSIS is to fabricate the chip – they will run their own DRC.

Sample error: DRC9_2 metal2 spacing = 3L Draw rectangle of metal2to fill gap It also called contact-to-contact metal 2 spacing DRC9_2 error

Layout vs schematic check using Calibre Interactive LVSCompare extracted transistor-level netlist against netlist saved in DA-ICFrom ICstation menu: Calibre > Run LVS In popup, Calibre location: $MGC_HOME/../Calibre Rules: $ADK/technology/ic/process/tsmc035.calibre.rulesInput: count4.src.net (previously created in DA-IC) H-cells: $ADK/technology/adk.hcell (hierarchical cells) Extracted file: count4.lay.net

Post-layout parameter extraction via Calibre Interactive PEX Extract Spice netlist, including parasitic RC Simulate in Eldo or MachTAICstation menu: Calibre >Run PEX Options similar to Calibre LVSExtraction options: lumped C + coupling cap’sdistributed RCdistributed RC + coupling cap’sOutput file: count4.pex.netlist

Post-layout simulation with MachTA MachTA is an accelerated Spice simulator Digital & mixed-signal circuits Analyze timing effects pre- and post-layoutSPICE netlists with parasitic R/C Execute test vector file to verify functionalityAlgorithms support large designs Partition design, simulate only partitions with changesCombine time-driven & event-driven operation Solves linearized models using a proprietary high-performance, graph-theory based, matrix solution algorithm

Mach TA flow diagram SPICE netlist $ADK/technology/mta/tsmc035

Prepare Calibre-extracted netlist for Mach TA ( file.pex.netlist )In file.pex.netlist, insert model definitions and VDD/GND voltage source functions after comment header: * File: m7.pex.netlist* Created: Thu Nov 15 15:25:56 2007* Program "Calibre xRC" * Version "v2005.2_9.14".model n nmos.model p pmos Vvdd VDD 0 5Vgnd GND 0 0Delete (or comment out with * in 1 st column) .subcircuit statement and any continuation lines (for long statement): *.subckt modulo7 CLK Q[1] CLEARBAR I[1] Q[0] I[0] Q[2] *+ L_CBAR I[2] GND VDDChange .ends to .END near end of file

Post-layout simulation with Mach TA Invoke Mach TA: ana - command file to initialize Anacad SW mta –ezw –t $ADK/technology/mta/tsmc035 count4.sp Other options: -do file (execute commands from file.do – instead of design.spdo -donot (run without simulating – compile only) -b (run in batch mode – no GUI – output to console) Transistor calibration files for this technology Generate waveform database & display in EZwave Netlist, modified as on previous slide

Sample Mach TA “dofile” (transient analysis) plot v( clk) v(q[2]) v(q[1]) v(q[0])measure rising TRIG v( clk) VAL=2.5v RISE=1 TARG v(q[0]) VAL=2.5vl loadl reset h countl clkrun 5 ns h reseth clkrun 5 ns l clkrun 5 ns h clk run 5 ns Signals to observe in EZwave Measure time from rising edge of clk (TRIGger) to 1st rising edge of q[0] (TARGet) - voltages Drive signals low/high ( Lsim format) Simulate for 5 ns Command to execute: dofile file.do

EZwave waveform viewer (results for previous dofile) Double-click signal name to display.

Alternative Mach TA “dofile” (same result as previous example) plot v( clk) v(q[2]) v(q[1]) v(q[0]) measure rising TRIG v(clk) VAL=2.5v RISE=1 TARG v(q[0]) VAL=2.5vvpulse Vclk clk 0 pulse(0 3.3 10n .05n .05n 10n 20n)l loadl reset h countrun 5 nsh resetrun 200 ns Voltage source name Nodes to which source connected v-levels delay rise fall width period Periodic pulses

Mach TA – test vector file Verify design functionality/behavior apply test vectors capture outputscompare outputs to expected resultuse vectors/outputs from behavioral simulation Command to execute a test vector file:run –tvend tvfile.tv test vector file (next slide)

Test vector file format # Test vector file for modulo7 counter CODEFILE UNITS ps RISE_TIME 50FALL_TIME 50INPUTS clk,reset,load,count,i[2],i[1],i[0]; OUTPUTS q[2] (to=max),q[1] (to=max),q[0] (to=max);CODING(ROM)RADIX <11113>3; @0 <01105>X;@2000 <00105>0;@7000 <01105>0;@10000 <11105>5; @20000 <01015>5;@30000 <11015>6; @40000 <01015>6;@50000 <11015>0; @60000 <01015>0;….. END Header Vectors: @time <input_vector>expected_output Sample 5 fs before next vector signal order within vectors Test vectors derived from behavioral simulation results Vector format

Behavioral simulation listing Corresponding Mach TA test vector file

Alternate test vector file (clock generated separately by voltage source) vpulse vclk clk 0 pulse(0 3.3 10n .5n .5n 10n 20n) Can mix other simulationcommands with test vectorapplication.

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Top level layout design flow** Create a symbol for each core block ( adk_daic)Create a chip-level schematic from core blocks and pads ( adk_daic)Generate design viewpoints (adk_dve) Create a layout cell for the chip(adk_ic)Place core logic blocks from the schematic Generate a pad frameMove/alter core blocks to simplify routingRoute pads to core blocksDesign rule check & fix problemsGenerate mask data ** Refer to on-line tutorials by Yan/Xu and by Dixit/Poladia

Chip-level schematic (1) Generate a symbol for each “core” logic block In DA-IC, open the schematic (eg. modulo7)Select: Miscellaneous > Generate SymbolAdd “phy_comp” property to the symbolSelect the body of the symbolFrom the popup menu: Properties > AddEnter property name: phy_compEnter property value: mod7b (layout cell name for the block created in IC Station)Check & save Example on next slide

Symbol with phy_comp property Layout cell is “mod7b” for logic schematic“modulo7”

Chip-level schematic (2) In DA-IC, create a schematic for the chip Instantiate core blocks Menu pallete: Add > InstanceSelect and place generated symbolAdd pads from ADK Library>Std. Cells>Pads >tsmc035 : In, Out, BiDir, VDD, GND Wire pads to logic blocks and connectorsAssign pin numbers, if knownChange pad instance name to PINdd (dd = 2-digit pin #)Check & saveCreate design viewpoints with adk_dve Example on next slide

Assigning PAD pin numbers Change instance name property on pads to PINxx xx = 2-digit pin number (01 – 40 for Tiny Chip package) Place pad on chip pin 01 Default instancenames

Top-level schematic for “modulo7” chip Hierarchical connectors on “Pad” pins Wire block I/O pins to pad signal pins VDD/GND Pads Core block Instance name =PINxx (chip pin #)

Chip layout Start IC Station (adk_ic) & create a new layout cell enter cell name logic source is “layout” viewpoint of chip schematicsame library, process file, rules file, and options as standard cell layoutOpen the schematic ADK Edit menu: Logic Source > OpenIn the schematic, select all core cells (but not pads)Place the cells: Place > InstGenerate the pad frameTop menu bar: ADK > Generate Padframe > tsmc035

Chip layout (2) Move, rotate, flip core logic cells as desired to make routing easier BUT - DO NOT EDIT OR MOVE PAD CELLS Autoroute all connections Select autoroute all on P&R menu Click “options” on prompt bar, and unselect “Expand Channels” (prevents pads from being moved)Add missing VDD/GND wires, if necessaryAutorouter might only route 1 VDD/GND wire, even if multiple VDD/GND padsManually add others: Objects>Add>PathVDD/GND net width = 50VDD/GND net vias = 6x6 (copy an existing via)

Modulo-7 counter in pad frame