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Design of Sparse Filters for Channel Shortening Design of Sparse Filters for Channel Shortening

Design of Sparse Filters for Channel Shortening - PowerPoint Presentation

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Design of Sparse Filters for Channel Shortening - PPT Presentation

Aditya Chopra and Prof Brian L Evans Department of Electrical and Computer Engineering The University of Texas at Austin 1 Introduction Finite Impulse Response FIR model of transmission media ID: 401175

channel equalizer shortening sparse equalizer channel sparse shortening complexity design introduction analysis results delay data runtime communications filter length

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Slide1

Design of Sparse Filters for Channel Shortening

Aditya Chopra and Prof. Brian L. EvansDepartment of Electrical and Computer EngineeringThe University of Texas at Austin

1Slide2

Introduction

Finite Impulse Response (FIR) model of transmission mediaSignal distortion during transmission Frequency selectivity of communicating mediumMultipath and reverberation Typically referred to as ‘channel’Channel delay spreadDuration of time for which channel impulse response contains significant energy

Large delay spread may be detrimental to high-speed communications

Leads to inter-symbol interference

[Bingham, 1990]

2

Introduction

| Channel Shortening | Sparse Equalizer | Complexity Analysis | Results Slide3

Introduction

Discrete Multi-Tone (DMT) ModulationTypically used in high-speed wireline communications (eg. ADSL)Data transmission in parallel over multiple carriersCyclic prefix (CP) is used to combat ISIEffective if channel delay spread shorter than CP length

3

DATA

CYCLIC PREFIX

DATA

CYCLIC PREFIX

Introduction

| Channel Shortening | Sparse Equalizer | Complexity Analysis | Results Slide4

Channel Shortening

Signal processing algorithms designed to reduce delay spreadEqualizer design to reduce delay spread of combined channel and shortening filter4

Channel

Shortening Equalizer

LARGE DELAY SPREAD

REDUCED DELAY SPREAD

Introduction |

Channel Shortening

| Sparse Equalizer | Complexity Analysis | Results Slide5

Channel Shortening Equalizer Design

Maximum shortening SNR criterion [Martin et al., 2005]

Shortening SNR (SSNR) defined as ratio of channel energy within cyclic prefix to channel energy outside cyclic

prefix of length

For a discrete time channel

Design Problem

Design equalizer

constrained to length

to maximize SSNR of

 

5

Introduction |

Channel Shortening

| Sparse Equalizer | Complexity Analysis | Results Slide6

Channel Shortening Equalizer Design

Optimal solution [Melsa et al., 1996]

is the eigenvector corresponding to minimum eigenvalue of

and

are

Toeplitz

matrices corresponding to vectors

and

respectively

 

6

Introduction |

Channel Shortening

| Sparse Equalizer | Complexity Analysis | Results Slide7

FIR filters with non-consecutive non-zero tapsTypically referred to as sparse filters

Larger delay spread than dense filters Filtering requires same complexity as dense filter with equal number of non-zero tapsE.g. RAKE receiver structure in CDMA communicationsSparse Filters7

DENSE EQUALIZER

SPARSE EQUALIZER

Introduction | Channel Shortening |

Sparse Equalizer

| Complexity Analysis | Results Slide8

Sparse Equalizer Design

Design problemDesign equalizer , constrained to

non-zero taps and maximum delay of

,

to maximize SSNR of

Optimal solution (exhaustive search)

Define a set

of indexing matrices

Design

using

and

is the equalizer

with highest SSNR

 

8

Introduction | Channel Shortening |

Sparse Equalizer

| Complexity Analysis | Results Slide9

Low Complexity Equalizer Design

‘Strongest tap selection’ methodDesign large length dense filter and choose a subset of strongest tapsDesign sparse filter on the selected locations

Features

Suboptimal

Lower computational complexity than optimal design methodSimilar approach used in G-RAKE receiver

[Fulghum

et al.

,2009

]

9

DENSE EQUALIZER

CHOOSE STRONGEST TAPS

REDESIGN SPARSE EQUALIZER

Introduction | Channel Shortening |

Sparse Equalizer

| Complexity Analysis | Results Slide10

Computational Complexity Analysis

Design + Runtime model of communicationModem performs channel estimation and equalizer design during initial training stageEqualizer coefficients are stored and used during data transmissionAssumption: Data transmission duration is much longer than training10

Introduction | Channel Shortening | Sparse Equalizer |

Complexity Analysis

| Results

L

: NUMBER OF NON-ZERO TAPS

M

: MAX FILTER DELAY

R

: SAMPLING RATE

TEQ Stage (Equalizer

type)

Computational

Complexity (Multiplications)Design (Original)

Design

(Sparse – Exhaustive)

Design

(Sparse – Heuristic)

Runtime

TEQ Stage (Equalizer

type)

Computational

Complexity (

Multiplications)

Design (Original)

Design

(Sparse – Exhaustive)

Design

(Sparse – Heuristic)

Runtime Slide11

Simulation Parameters

Simulate sparse equalizers on Carrier Serving Area Loop channel modelsTypically used in DMT11Introduction | Channel Shortening | Sparse Equalizer | Complexity Analysis |

Results

Parameter

Value

Sampling Rate

2.208

MHz

Symbol Length

512 samples

Cyclic

Prefix Length

32 samples

Maximum

tap delay (M)

10

Channel Model

ADSL Carrier Serving Area Loop 1Slide12

Channel Shortening Performance

12Introduction | Channel Shortening | Sparse Equalizer | Complexity Analysis | Results

CHANNEL SHORTENING SNR PERFORMANCE VS. NUMBER OF NON-ZERO EQUALIZER TAPS

FOR CARRIER SERVING AREA LOOP 1 CHANNELSlide13

Comparison of computational complexity for various equalizer design methodsFilter Length is number of non-zero taps in equalizer

M = 10 for sparse equalizersDesign complexity is number of multiplication operationsDesign + Runtime complexity is multiplication operations required for filter design and 1 second of filter operation at R = 2.208 MHzComputation Complexity13

Equalizer Type

Filter Length

Design Complexity

Design + Runtime

Complexity

Dense

)

Sparse –

optimal

)

)

Sparse – heuristic

)

)

Equalizer Type

Filter Length

Design Complexity

Design + Runtime

Complexity

Dense

Sparse –

optimal

Sparse

– heuristic

Introduction | Channel Shortening | Sparse Equalizer | Complexity Analysis |

Results Slide14

Equalizer Design Tradeoff

14

CHANNEL SHORTENING SNR PERFORMANCE VS. DESIGN + 1 SEC. RUNTIME COMPLEXITY

FOR CARRIER SERVING AREA LOOP 1 CHANNEL

Introduction | Channel Shortening | Sparse Equalizer | Complexity Analysis |

Results Slide15

Summary

Sparse shortening equalizer designHigh computational complexity requirements for designFavorable for few non-zero coefficientsReconcile increased design computation by improved communication performance during data transmissionApplications

Channel shortening equalizers in ADSL systems

RAKE receivers in CDMA systems

Equalizers in underwater acoustic communications15

Introduction | Channel Shortening | Sparse Equalizer | Complexity Analysis |

Results Slide16

References

[Bingham1990] J. A. C. Bingham, “Multicarrier modulation for data transmission: an idea whose time has come,” IEEE Communications Magazine, vol. 28, no. 5, pp. 5–14, May 1990[Melsa1996] P. J. W.

Melsa

, R. C.

Younce, and C. E. Rohrs, “Impulse response shortening for discrete multitone transceivers,”

IEEE Transactions on Communications, vol. 44, no. 12, pp. 1662–1672, Dec. 1996

[

Fulghum2009

]

T.

Fulghum

, D. Cairns, C.

Cozzo, Y.-P. Wang, and G. Bottomley, “Adaptive generalized rake reception in ds-

cdma systems,”

IEEE Transactions on Wireless Communications, vol. 8, no. 7, pp. 3464–3474, Jul. 2009[Martin2005] R. K. Martin, K.

Vanbleu, M. Ding, G. Ysebaert, M. Milosevic, B. L. Evans, M. Moonen, and J. Johnson, “Unification and

evaluation of equalization structures and design algorithms for discrete multitone modulation systems,” IEEE Transactions on Signal Processing, vol. 53

, no. 10, pp. 3880–3894, Oct. 2005.

16Slide17

Thank you!

17