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Digital Logic Systems Digital Logic Systems

Digital Logic Systems - PowerPoint Presentation

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Digital Logic Systems - PPT Presentation

Combinational Circuits Basic Gates amp Truth Tables Basic Gates AND Gate OR Gate NOT Gate More Gates NAND Gate NOR Gate BUF Gate More Gates XNOR Gate XOR Gate nInput Gates 3Input XOR Gate ID: 618881

switching gate gates expressions gate switching expressions gates operation input xor true output logical truth functions tables inputs variables

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Slide1

Digital Logic Systems

Combinational CircuitsSlide2

Basic Gates

&

Truth TablesSlide3

Basic Gates

AND Gate

OR Gate

NOT GateSlide4

More Gates

NAND Gate

NOR Gate

BUF GateSlide5

More Gates

XNOR Gate

XOR GateSlide6

n-Input Gates

3-Input XOR Gate

5-Input NOR Gate

5-Input AND Gate

4-Input OR GateSlide7

Definitions

AND

It gives a logical output true only if all the inputs are true

OR

It gives a logical output true if any of the inputs is true

XOR

It gives a logical output true only if an odd-number of inputs is true

NOT

It gives a logical output true if the input is false and vice versaSlide8

Truth Table

A truth table is a tabular procedure to express the relationship of the outputs to the inputs of a Logical SystemSlide9

Truth Tables for Gates

a

b

f

AND

0

0

0

0

1

0

1

0

0

1

1

1

a

b

f

OR

0

0

0

0

1

1

1

0

1

1

1

1

a

f

NOT

0

1

1

0

AND Operation

OR Operation

NOT Operation

AND Gate

OR Gate

NOT GateSlide10

Truth Tables for Gates

a

b

f

NAND

0

0

1

0

1

1

1

0

1

1

1

0

a

b

f

NOR

0

0

1

0

1

0

1

0

0

1

1

0

a

f

BUF

0

0

1

1

NAND Operation

NOR Operation

BUF Operation

NAND Gate

NOR Gate

BUF GateSlide11

Truth Tables for Gates

a

b

f

XOR

0

0

0

0

1

1

1

0

1

1

1

0

a

b

f

XNOR

0

0

1

0

1

0

1

0

0

1

1

1

XOR

Operation

XNOR

Operation

XNOR Gate

XOR GateSlide12

A Bubble Implies a Logical Inversion

Bubbles can be replaced by NOT Gates to get logically equivalent circuits

BubblesSlide13
Slide14
Slide15
Slide16
Slide17
Slide18
Slide19
Slide20
Slide21
Slide22

Generate tables for all combinations of bubbles and a XOR gateSlide23

Gate Equivalence

=

=

=Slide24

Gate Equivalence

=

=

?Slide25

Gate Equivalence

=

=Slide26

Switching ExpressionsSlide27

Basic Switching Expressions

AND

f = a . b

OR

f = a + b

NOT

f = a’

f = āSlide28

Is there an expression for XOR operation?Slide29
Slide30
Slide31

Switching ExpressionsSlide32

Switching ExpressionsSlide33

Switching Expressions

f

1

= a . b’

f

2

= (a + b)’Slide34

Switching ExpressionsSlide35

Switching ExpressionsSlide36

Switching Expressions

f = ? Slide37

Switching Expressions

f = m + n

n = a’ . b

m = a . b’Slide38

Switching Expressions

f = (a . b’) + (a’ . b)

This is the equivalent circuit and equivalent expression for a XOR operation Slide39

From

Digital Design, 5th 

Edition

by M. Morris Mano and Michael

Ciletti

Slide40

Switching ExpressionsSlide41

Switching ExpressionsSlide42

Switching Expressions

f

1

= a . b

f

2

= a ^ b

f

2

= (a . b’) + (a’ . b)Slide43

Switching ExpressionsSlide44

x

y

z

p = x ^ y

g = x . y

m = p . z

s = p ^ z

c = m + g

0

0

0

 

 

 

 

 

0

0

1

 

 

 

 

 

0

1

0

 

 

 

 

 

0

1

1

 

 

 

 

 

1

0

0

 

 

 

 

 

1

0

1

 

 

 

 

 

1

1

0

 

 

 

 

 

1

1

1

 

 

 

 

 Slide45

x

y

z

p = x ^ y

g = x . y

m = p . z

s = p ^ z

c = m + g

0

0

0

0

0

 

 

 

0

0

1

0

0

 

 

 

0

1

0

1

0

 

 

 

0

1

1

1

0

 

 

 

1

0

0

1

0

 

 

 

1

0

1

1

0

 

 

 

1

1

0

0

1

 

 

 

1

1

1

0

1

 

 

 Slide46

x

y

z

p = x ^ y

g = x . y

m = p . z

s = p ^ z

c = m + g

0

0

0

0

0

0

 

 

0

0

1

0

0

0

 

 

0

1

0

1

0

0

 

 

0

1

1

1

0

1

 

 

1

0

0

1

0

0

 

 

1

0

1

1

0

1

 

 

1

1

0

0

1

0

 

 

1

1

1

0

1

0

 

 Slide47

x

y

z

p = x ^ y

g = x . y

m = p . z

s = p ^ z

c = m + g

0

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

1

0

1

0

0

1

0

0

1

1

1

0

1

0

1

1

0

0

1

0

0

1

0

1

0

1

1

0

1

0

1

1

1

0

0

1

0

0

1

1

1

1

0

1

0

1

1Slide48

x

y

z

s

c

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1Slide49

s = s

c = m + g Slide50

s = s

c = m + g

m = p . z

g = g

s = p ^ zSlide51

s = s

c = m + g

m = p . z

g = g

p = x ^ y

g = x . y

s = p ^ zSlide52

s = s

c = m + g

p = x ^ y

g = x . y

m = (x ^ y) . z

g = g

s = (x ^ y) ^ zSlide53

s = (x ^ y) ^ z

c = ((x ^ y) . z)

+ (x . y)

p = x ^ y

g = x . y

m = (x ^ y) . z

g = g

s = (x ^ y) ^ zSlide54

s = (x ^ y) ^ z

c = ((x ^ y) . z) + (x . y)Slide55

s = ((x

. y

’) + (x’ . y)) ^ z

c = (((x . y’) + (x’ . y)) . z) + (x . y)Slide56

s = (((x . y’) + (x’ . y))’ . z) + (((x . y’) + (x’ . y)) . z’)

c = (((x .

y’)

+ (x’ . y)) . z) + (x . y)Slide57

Procedure

To obtain the output functions from a logic diagram, proceed as follows:

Label with arbitrary symbols all gate outputs that are a function of the input variables. Obtain the Boolean Functions for each gate.

Label with other arbitrary symbols those gates that are a function of input variables and/or preciously labeled gates. Find the Boolean functions of these gates.

Repeat the process in step 2 until all the outputs of the circuit are obtained.

By repeated substitution of previously defined functions, obtain the output Boolean functions in terms of input variables only.Slide58
Slide59