Mo deling and Analysis of Di eren tial Signaling for Minimizing Inductiv e CrossT alk ehiaMassoud JamilKa DonMacMillen JacobWhite Adv ancedT ec h PDF document - DocSlides

Mo deling and Analysis of Di eren tial Signaling for Minimizing Inductiv e CrossT alk ehiaMassoud JamilKa DonMacMillen JacobWhite Adv ancedT ec h PDF document - DocSlides

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Group Adv ancedT ec hGroup Adv ancedT ec hGroup EECSDept SynopsysInc SynopsysInc SynopsysInc MIT Moun tainViewCA Moun tainViewCA Moun tainViewCA Cam bridgeMA Abstract Man yph ysical syn thesis to ols in terdigitate signal and p o er lines to reduce c ID: 23440

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Presentations text content in Mo deling and Analysis of Di eren tial Signaling for Minimizing Inductiv e CrossT alk ehiaMassoud JamilKa DonMacMillen JacobWhite Adv ancedT ec h


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Mo deling and Analysis of Di eren tial Signaling for Minimizing Inductiv e Cross-T alk ehiaMassoud JamilKa DonMacMillen JacobWhite Adv ancedT ec h.Group Adv ancedT ec h.Group Adv ancedT ec h.Group EECSDept. SynopsysInc. SynopsysInc. SynopsysInc. MIT Moun tainView,CA Moun tainView,CA Moun tainView,CA Cam bridge,MA Abstract Man yph ysical syn thesis to ols in terdigitate signal and p o er lines to reduce cross-talk, and th us, impro e signal in tegrit and timing predictabilit .Suc h approac hes are extremely e ectiv e at reducing cross-talk at circuit sp eeds where in- ductiv e e ects are inconsequen tial . In this pap er, w euse a detailed distributed RLC mo del to sho w that inductiv cross-talk e ects are substan tial in long busses asso ciated with 0.18 micron tec hnology . Sim ulation exp erimen ts are then used to demonstrate that cross-talk in suc h high sp eed tec hnologies is m uc h b etter con trolled b y re-deplo ying in ter- digitated p o er lines to p erform di eren tial signalin g. Intro duction In deep sub-micron (DSM) tec hnologies, critical feature size con tin ues to shrink and no w nearly 100 million transistors can b e pac ed in to a single die. The a ailabil i t y of man yla y- ers of lo w resistance metal (Cu) in terconnects mak es routing of suc h complex c hips p ossible, but demand for higher sys- tem p erformance reduces timing slac ks and puts added con- strain ts on timing accuracy and predictabili t . This mak es the optimization of in terconnects extremely dicult. T yp- ically , p erformance is ac hiev ed b y routing global in tercon- nects using upp er metal la ers and wide metal lines to reduce resistance. T ok eep resistance lo w, top metal la er thic kness ha e not scaled with new er tec hnologies, whic h has led to an increase in coupling capacitance, and therefore, has cre- ated cross-talk problems. T o reduce coupling b et een adja- cen t lines the commonly used tec hniques are widening metal lines, shielding, bu er insertion, and increasing the wire to wire spacing. These tec hniques, esp ecially shielding , handle capacitiv e coupling noise problems v ery successfully In the next section, w eev aluate the noise c haracteris- tics of standard cross-talk a oidance strategies includin g: shielding , widening metal lines, increasing wire separation, and bu er insertion. R C mo dels of the in terconnect are an- alyzed rst then inductiv e e ects are included to sho w that in 0.18 micron tec hnology ,andbey ond, inductance has a rst order e ect on cross-talk noise. Assuming the same set of timing constrain ts applies for all strategies, w esho that standard cross-talk a oidance strategies are of limited e ectiv eness. In section 3, w e presen t results on using dif- feren tial signaling , and sho w that suc hanapproac hism uc more e ectiv e at reducing cross-talk when inductiv e e ects are included. In section 4, w e compare the p erformance of di eren tial signaling to shielding as a means of reducing cross-talk noise, and sho w that di eren tial signaling has m uc h sup erior noise haracteristics ev en for m uc htigh ter timing budgets than other standard cross-talk a oidance strategies. In section 5, e sho w that di eren tial signaling sup eriorit y in noise re- duction is due to its insigni ca n t noise radiation, and also, due to its sup erior noise imm unit Standa rd Cross-T alk Noise Reduction T echniques or our sim ulation and analysis, w e used a ma jor foundry's 18 pro cess. The metal lines w ere implemen ted in metal 6 with all lines ha ving a metal width of 3 and a metal to metal spacing of 1 consisten twitht ypical high lev el metal implemen tations of high p erformance global busses. The only exception to that are the test cases where the metal width or the metal spacing w as in ten tionall y v aried as part of the exp erimen t. In all exp erimen ts, w e sandwic hed the data bus b et een a VDD line and a VSS line eac h15 wide to pro vide a return path for the curren t o wing in the buses. In all test cases, w e used simple bu ers (scaled in ert- ers) for driv ers and receiv ers implemen tation in the standard cases, and a di eren tial driv er-receiv er pair for the imple- men tation of di eren tial examples. In order to b e consisten in our comparison b et een the v arious cases considered, w main tained the same timing constrain t of a propagation de- la y of 0.35ns from input to output. ealw ys used the eak est driv ers sucien t for meeting that timing constrain in all the test cases to mak e sure that the driv ers are not themselv es a source of noise. Also, w e main tained an input capacitance of appro ximately 10 . All receiv ers w ere loaded with a mo derate load of 0.1pf. e used a distributed RLC [1] mo del to mo del the in ter- connects where F astCap [2] w as used to mo del the in tercon- nect capacitance and F astHenry [3] w as used to mo del b oth the resistance and the inductance of the in terconnects. In order to test for the w orst case noise generated on the 8-bit data bus, 3000 long, standard single ended bus sho wn in Figure 1, w e applied a 50 psec rise time step to all the inputs except the one in the middle. In Figure 3, sim- ulation results using Hspice[9] sho ws a totaly unacceptable
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IN2 OUT2 quiet line OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT1 OP1 IN1 IN3 IN4 IN5 IN6 IN7 IN8 Figure 1: A 8-bit global bus 3000 long. Metal line width =3 , metal line to metal line spacing =1 .The bus is sandwic hed b et een a VDD line and a VSS line eac 15 wide. The driv er and receiv er of eac h line is a standard CMOS bu er. OP1 VDD VDD VDD GND VDD quite line IN1 IN2 IN3 IN8 IN7 IN6 IN5 IN4 GND GND GND OUT4 OUT5 OUT6 OUT7 OUT8 OUT3 OUT2 OUT1 Figure 2: A 8-bit global bus 3000 long. Metal line width =3 , metal line to metal line spacing =1 shield line of alternating VSS/VDD connectivit y is inserted bet een alternating signal lines. oltage glitc h of 1.17V. Suc h a glitc h could cause erroneous switc hing and logic failures. In order to solv e this cross-talk noise problem, w e tested the most p opular cross-talk noise reduction tec hniques against this example. 2.1 Shielding T echnique Shieldin g is one of the most successful existing noise reduc- tion tec hniques [4,5]. The tec hnique, as sho wn in Figure 2, in terdigitates signal lines with Vdd or Vss alternativ ely .Fig- ure 3 sho ws that ev en when w e use the shielding tec hnique, av oltage glitc h of 0.54V will still app ear. Figure 4 sho ws that when the inductance is not mo deled, the shielding tec h- nique app ears to solv e the cross-talk problem p erfectly as only a 0.03V v oltage glitc h is generated. This is b ecause the shieldin g tec hnique is capable of screening signal lines and th us eliminating capacitiv e coupling. Ho ev er, due to the long range of curren t return paths, shielding is capable of screening only part of these signals curren t return paths, and th us shielding migh t eliminate only part of the inductiv coupling. 2.2 Widening Metal Lines Widening signal metal width is one the tec hniques that is mainly used to reduce capacitiv e cross-talk noise b y increas- 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Time (ns) 1.0 1.5 2.0 2.5 Voltage (V) Figure 3: Solid graph represen ts the noise signal in the shielded example measures at OP1 in Figure 2 (p eak noise=0.54V). Dotted graph represen ts the noise signal in the standard single ended example measured at OP1 in Fig- ure 1 (p eak noise=1.17V). Note that the inductance of the in terconnect is mo deled. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Time (ns) 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 Voltage (V) Figure 4: Solid graph represen ts the noise signal in the shielded example measures at OP1 in Figure 2 (p eak noise=0.03V) when the inductance of the in terconnect is not mo deled. Dotted graph represen ts the noise signal in the standard single ended example measured at OP1 in Fig- ure 1 (p eak noise=0.59V) when the inductance of the in ter- connect is not mo deled. ing the signal capacitance to the ground. Figure 5 sho ws that the generated noise w as reduced b y not more than 20% after the wire width w as increased from 3 to 7 .Inthis example w eha e widened the in terconnects and k ept the separation distance, S, at 1 so that the total area tak en y the data bus is the same as the one used in the shielding tec hnique. Other than this mo dest noise impro emen t, this tec hnique tends to increase the dela y as the area capacitance increases. 2.3 Increasing Metal to Metal Sepa ration Increasing the separation distance b et een signal lines is a ery w ell kno wn tec hnique to reduce cross-talk noise. In order to test this metho d, w e sim ulated the con guration sho wn in Figure 1 where w ek ept the signal width at 3 and increased the separation distance, S, suc h that the total area consumed b y the structure will b e the same as the one con- sumed b y shielding. Figure 6 sho ws that the generated noise as reduced to 0.82V. This is not as go o d as the shielding tec hnique. Note that when neglecting the inductance, this tec hnique reduced the cross-talk noise to 0.21V whic hsho ws that this tec hnique can b e successful if no inductiv e coupling is in olv ed. This is due to the fact that although when in- creasing line separation, capacitiv e coupling decreases with
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0.0 0.5 1.0 1.5 2.0 2.5 3.0 Time (ns) 1.0 1.5 2.0 2.5 Voltage (V) Figure 5: Noise signal measured at OP1 in Figure 1 for a big- ger width =7 and =1 . Solid graph represen ts noise when inductance is NOT mo deled(p eak noise=0.47V). Dotted graph represen ts noise when inductance is mo deled (p eak noise=0.94V). 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Time (ns) 1.0 1.5 2.0 2.5 Voltage (V) Figure 6: Noise signal measured at OP1 in Figure 1 for a big- ger spacing =3 and =5 . Solid graph represen ts noise when inductance is NOT mo deled (p eak noise=0.21V). Dotted graph represen ts noise when inductance is mo deled (p eak noise=0.82V). distance, lo op inductance increases, and th us the tec hnique fails. 2.4 Bu er Insertion T echnique Bu ers are often inserted in long in terconnect routes to re- duce cross-talk noise[6]. Bu er insertion t ypically reduces cross-talk noise but often degardes the p erformance due to the additional dela ys of the inserted bu ers. In order to test the bu er insertion metho d with the standard single-ended bus con guration in Figure 1, w e divided eac hin terconnect line in the bus in to t o1500 segmen ts with a bu er in- stered in b et een the t o segemnets. W e used the w eak est bu ers and driv ers to meet our dela y target of 0.35ns. Fig- ure 7 sho ws that the generated cross-talk noise w as reduced to 0.87V whic hisw orse than that of the shieldin g tec hnique. When inserting t o bu ers instead of one bu er in eac hin- terconnect line of the bus in gure 1, the dela y has dete- riorated signi can tl y and the dela y constrain t could not b e met. Ev en when doubling the dela y constrain t to 0.7ns, the cross-talk noise w as 0.62V whic hisstill w orse than shieldin g. Di erential Signaling As w e discussed in section 2, all of the standard noise re- duction tec hniques failed to giv e satisfactory noise reduction 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Time (ns) 1.0 1.5 2.0 Voltage (V) Figure 7: Noise signal measured at OP1 in Figure 1 with eac hin terconnect line in the bus is divided in to t o1500 segmen ts with a bu er instered in b et een the t o segem- nets. Solid graph represen ts noise when inductance is NOT mo deled (p eak noise= 0.43V). Dotted graph represen ts noise when inductance is mo deled (p eak noise=0.87V). results for a high p erformance global bus. This w as mainly due to the presence of inductance in this problem and these tec hniques are more suited for capacitance dominated prob- lems. Recen tly [7], there has b een increased in terest in lo swing signaling, but inductiv e e ects ha e not b een included in previous studies. In this section w e will discuss the use of limited swing di eren tial signaling and ho w it can signif- ican tly reduce cross-talk noise. 3.1 Circuit Implementation fo r the di erential transmitter and reciever The di eren tial driv er used is sho wn in Figure 8, The driv er consists of a v ery lo w input capacitance in erter and of a transmission gate generating a balanced dela ysignaland signal-bar that driv et o matc hed bu ers generating the dif- feren tial signal. The bu ers are simple in erters with activ curren t feedbac k in the form of an alw ys -on transmission gate. The bu er with the feedbac kisessen tially a simple op-amp with a virtual grounded input and a lo wv oltage gain. The activ e feedbac k pro vides maxim um exibilit yin con trolling the dela , swing, and cen tering of the di eren tial signal with resp ect to vdd and gnd. Also the v ery lo winput capacitance of the pre-driv er mak es this driv er v ery useful in tigh t timing budgets and shallo w pip eline arc hitectures. Similar driv ers ha e b een used for v ery high frequency RF application s [8]. The driv er w e implemen ted had a swing of 300mV with a lo wlev el of 0.7V and a high lev el of 1.0V. The input capacitance of the driv er w as 10 . The receiv er, sho wn in Figure 9, w as a standard static di eren tial receiv er with a lo w imp edance curren t source for stabilit y against in- jected noise and it dro e a load of 100 (ten standard loads equiv alen t). 3.2 Di erential Bus enext in estigated the use of di eren tial signaling for the whole bus, as sho wn in Figure 10, and w e observ ed the out- puts OP1 and OP2 of the "quiet" di eren tial signal and signal-bar in the middle of the bus at the end of the 3000 di eren tial line. Figure 11 sho ws that the t o p oin ts OP1 and OP2 are almost alw ys in phase. This mak es the dif- ference OP1-OP2 v ery small. This di erence is the e ectiv noise seen b y the di eren tial receiv er. Figure 12 sho ws that y using this di eren tial bus the e ectiv e noise seen at the
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IN Gnd Gnd Gnd Vdd Vdd Vdd OUT OUTB Figure 8: Limited Swing Di eren tial T ransmitter OUT V- Gnd Vdd V+ R=50 Figure 9: Di eren tial Receiv er quiet line OUT5 IN5 OUT6 IN6 OUT7 IN7 OUT8 IN8 OUT3 IN3 OUT4 IN4 OUT2 IN2 IN1 OUT1 quiet line OP1 OP2 AMP AMP AMP AMP AMP AMP AMP AMP Figure 10: A 3000 long global bus with 8-bits di eren- tial. The driv er of the di eren tial signals is a limited swing di eren tial driv er and the receiv er is a di eren tial receiv er. Metal line width =3 , metal line to metal line spacing =1 . The 16 line bus is sandwic hed b et een a VDD line and a VSS line eac h15 wide. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Time (ns) 0.70 0.75 0.80 0.85 0.90 0.95 1.00 Voltage (V) Figure 11: The signal on p oin ts OP1 and OP2 of the di er- en tial receiv er in Figure 10. input of the di eren tial receiv er is only 53m v p eak, th us, re- ducing the cross-talk noise b y more than one order of mag- nitude compared with an y of the cross-talk noise reduction tec hniques discussed in section 2. Timing and Noise Compa rison b et een di erential sig- naling and shielding In this section, w e compare the p erformance of di eren tial signaling to shielding, ha ving sho wn in section 2 that shield- ing is the most e ectiv e among the standard noise reduction tec hniques. In the previous t o sections, w esho ed that when main taining the same timing constrain t of a propa- gation dela y of 0.35ns on the global data bus, the di eren- tial bus exerted a w orst case cross-talk noise of only 53m v. Th us, b y using this di eren tial bus, the cross talk noise w as reduced b y more than 10 times compared to the shielding tec hnique. In order for the shielding tec hnique to pro duce a b etter noise p erformance, the dela y constrain t on the data bus has to b e further relaxed. F or example: the dela y con- strain t has to b e tripled to 1.05 nsec in order for the noise sho wn on the shielded bus to b e 60m vwhic h is still more than that of the di eren tial bus. Th us, b y using this dif- feren tial bus, whic htak es no more area than that used b the shieldin g tec hnique, the cross-talk noise w as reduced b
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0.0 0.5 1.0 1.5 2.0 2.5 3.0 Time (ns) 220 230 240 250 260 270 280 290 300 310 320 Voltage (mV) Figure 12: The di erence b et een the signals on p oin ts OP1 and OP2 of the di eren tial in Figure 10. This represen ts the input noise signal to the di eren tial receiv er (maxim um cross-talk noise is only 53m v). OP1 OUT3 IN3 OUT2 IN2 IN1 OUT1 IN4 OUT4 IN8 OUT8 IN7 OUT7 IN6 OUT6 IN5 OUT5 quiet line AMP AMP AMP AMP AMP AMP AMP Figure 13: A 8-bit global bus with 7-bits di eren tial (14 signal lines) 3000 long. =3 =1 . The non- di eren tial (standard) bit signal is placed in the middle of the di eren tial signals. more than an order of magnitude for the same timing con- strain t. Also, the di eren tial bus still pro duced a b etter noise p erformance o er the standard shielded bus ev en when the timing budget for the standard shielded bus w as tripled. Why Di erential Signaling is sup erio e devised t o exp erimen ts to sort out if di eren tial sig- naling is go o d b ecause it is inheren tly imm une to noise or b ecause it do es not radiate signi can t electromagnetic in ter- ference that can disturb neigh b ors. 5.1 Lo w Noise Generation Figure 13 sho ws a setup where the bus is driv en di eren- tially .Ho ev er, the "quiet" line in the cen ter is standard single ended. W eobserv ed the output (OP1) of the quiet line with the remaining 7 di eren tial pairs switc hing. Figure 14 sho ws the quiet line to ha e a cross-talk noise p eak of 38mV, whic h asserts that di eren tial signaling do es not radiate sig- ni can t electromagnetic in terference. This is mainly b ecause a di eren tial transmitter needs to driv e a load to a v oltage swing of less than 300m v, compared to 1.8V for a standard driv er. Therefore for the same latency , di eren tial driv ers tend to b e m uc h smaller than standard driv ers, whic h results in a signi can tl y lo er di/dt, and therfore lo er inductiv noise generated. This has sp ecial p ositiv e implication s. It mak es routing di eren tial signals o er sensitiv e areas suc 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Time (ns) 1.765 1.770 1.775 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 1.825 Voltage (V) Figure 14: The noise signal on p oin t OP1 in Figure 13. (p eak noise is only=38m v). quiet line IN8 IN7 IN6 IN5 IN4 IN3 IN1 OP1 OUT1 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT2 IN2 quiet line OP2 OP3 Figure 15: An 8-bit, 3000 long, global bus of 7 standard signals and a di eren tial signal lo cated in the cen ter of the bus. =3 =1 . The bus is sandwic hed b et een a VDD line and a VSS line. The driv er of the di eren tial signal is a limited swing di eren tial driv er and the receiv er is a di eren tial receiv er. The driv ers and receiv ers of all the standard bits are standard CMOS bu ers. as RAMS p ossible. Generally , routing o er a RAM blo c kis prohibited for the fear of destructiv e coupling e ects. 5.2 Noise Immunit The second exp erimen t, sho wn in Figure 15, had all the switc hing signals standard non-shielded lines with the dif- feren tial signal in the middle as the quiet line. Although the single ended lines caused a high lev el of coupling on eac hof the di eren tial lines, OP1 and OP2, as sho wn in Figure 16, the t o di eren tial lines mo ed together k eeping the di er- ence b et een them not exceeding 83mV. This re ected an insigni ca n t 4mV on the di eren tial reciev er output, OP3, as sho wn in Figure 17. In order to compare the noise imm unit y of the di eren- tial with that corresp onding to the shielding, w e replaced the di eren tial bus in the middle of the single ended bus in Figure 15 with a regular standard single ended line along with a shielded line, as sho wn in Figure 18. Figure 19 sho ws av oltage cross-talk glitc h on the input of the standard single ended receiv er, OP1, of 1.12V, whic h re ected a nal out- put noise of 360mV on OP2 in Figure 18. This exp erimen pro es that di eren tial signalin g is m uc h more imm une to injected noise as the noise glitc hes on b oth the input and the output of the di eren tial receiv er w ere more than an order of magnitude less than the rep ectiv e glitc hes on the shielded single ended reciev er. This mak es di eren tial signaling a ery go o d solution for critical nets, as it pro vides sup erior noise imm unit y along with sp eed.
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0.0 0.5 1.0 1.5 2.0 2.5 3.0 Time (ns) 0.0 0.5 1.0 1.5 Voltage (V) Figure 16: The input signals to the di eren tial receiv er, OP1 and OP2 in Figure 15. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Time (ns) 0 50 100 150 200 250 Voltage (mV) Figure 17: Dotted graph represen ts the di erence b et een the signals on p oin ts OP1 and OP2 of the di eren tial re- ceiv er in Figure 15. This represen ts the input noise signal to the di eren tial receiv er (p eak input noise is 83m v). The solid graph represen ts the output of the di eren tial receiv er, OP3, in Figure 15. (p eak output noise is only 4m v). IN2 OUT2 quiet line OUT8 OUT7 OUT6 OUT4 OUT3 OUT1 OP1 IN1 IN3 IN4 IN6 IN7 IN8 GND (SHIELD) OP2 OUT5 IN5 Figure 18: An 8-bit global bus 3000 long. =3 . A grounded shield wire of width =3 is inserted in the middle of the bus. The bus is sandwic hed b et een a VDD line and a VSS line. The driv er and receiv er of eac line is a standard CMOS bu er. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Time (ns) 0.0 0.5 1.0 1.5 2.0 2.5 Voltage (V) Figure 19: Input and output noise signal to the middle stan- dard receiv er bu er in Figure 18. P eak noise on bu er input OP1=1.12V. P eak noise on bu er output OP2=360mV. Conclusions eha e sho wn that noise reduction tec hniques suc h as in- creased line separation, widening metal lines, bu er inser- tion, and shielding p erform w ell when only capacitiv e cou- pling is considered. Ho ev er, when inductiv e e ects are mo deled, sim ulations sho w there is still substan tial cross- talk. W e then demonstrated that lo w swing di eren tial sig- naling is b oth noise imm une and generates less electomag- netic noise. In this pap er, w eha e fo cused on the noise imm unit and noise generation issues in DSM in terconnect using lim- ited swing di eren tial signalin g. W esho ed that di eren- tial signalin g has sup erior noise c haracteristics with no area p enalt . Also, the fact that di eren tial signaling generates uc h less noise than standard cross-talk a oidance tec h- niques mak es it p ossible to route o er noise sensitiv e areas. References [1] A. Deutsc h et. al., " When are T ransmission-Line E ects Imp ortan t for On Chip In terconnections ?," IEEE T ransac- tion on MTT, v ol. 45, No 10, pp. 1836-1846, Octob er 1997. [2] K. Nab ors and J. White, " F astCap: A Multip ole - Accel- erated 3-D Capacitance Extraction Program," IEEE T rans- action on Computer-Aided Design , pp. 1447-1459, No em- b er 1991. [3] M. Kamon, M. Tsuk, and J. White, " F astHenry: A Multip ole-Accel erated 3-D Inductance Extraction Program," IEEE T ransaction on MTT, v ol. 42, No 9, pp. 1750-1758, Septem b er 1999. [4] Y. Massoud, S. Ma jors, T. Bustami, and J. White," La y- out T ec hniques for Minimizi ng On-Chip In terconnect Self Inductance," A CM/IEEE D C 1998. [5] S. Khatri, A. Mehrotra, R. Bra yton, A. Sangio anni - Vincen telli, and R. Otten," A No el VLSI La out F abric for Deep Sub-Micron Applications," A CM/IEEE D C 1999. [6] C. Alp ert, A. Devgan, and S. Qua , " Bu er Insertion for Noise and Dela y Optimization," A CM/IEEE D C 1998. [7] H. Zhang, V. George, and J. Rabaey ,"Lo w-Swing On- Chip Signaling T ec hniques: E ectiv eness and Robustness," IEEE T ransaction on VLSI Systems, v ol. 8, No 3, pp. 264- 272, June 2000. [8] H. Shin, D. Ho dges, "A 250-Mbit/s CMOS Crossp oin Switc h", IEEE Journal of Solid State Circuits, v ol 24, no.2, April 1989. [9] Hspice, Av an ti Corp oration, 2000.

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