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Read Disturb Errors - PowerPoint Presentation

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Read Disturb Errors - PPT Presentation

Read Disturb Errors in MLC NAND Flash Memory Characterization Mitigation and Recovery Yu Cai Yixin Luo Saugata Ghose Erich F Haratsch Ken Mai Onur Mutlu Carnegie Mellon University Seagate Technology ID: 769712

disturb read pass page read disturb page pass vpass flash errors error ecc memory cells oriented recovery problem experimental

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Read Disturb Errors in MLC NAND Flash Memory:Characterization, Mitigation, and Recovery Yu Cai, Yixin Luo, Saugata Ghose, Erich F. Haratsch*, Ken Mai, Onur MutluCarnegie Mellon University, *Seagate Technology

Executive SummaryRead disturb errors limit flash memory lifetime today Apply a high pass-through voltage (Vpass) to multiple pages on a readWe characterize read disturb on real NAND flash chipsSlightly lowering Vpass greatly reduces read disturb errors Some flash cells are more prone to read disturbTechnique 1: Mitigate read disturb errors onlineVpass Tuning dynamically finds and applies a lowered VpassFlash memory lifetime improves by 21%Technique 2: Recover after failure to prevent data lossRead Disturb Oriented Error Recovery (RDR) selectively corrects cells more susceptible to read disturb errorsReduces raw bit error rate (RBER) by up to 36% 2

OutlineBackground (Problem and Goal)Key Experimental ObservationsMitigation: Vpass TuningRecovery: Read Disturb Oriented Error Recovery Conclusion3

OutlineBackground (Problem and Goal)Key Experimental ObservationsMitigation: V pass TuningRecovery: Read Disturb Oriented Error RecoveryConclusion4

NAND Flash Memory Background Flash Memory Page 1 Page 0 Page 2 Page 255 …… Page 257 Page 256 Page 258 Page 511 …… …… Page M+1 Page M Page M+2 Page M+255 …… Flash Controller 5 Block 0 Block 1 Block N Read Pass Pass … Pass

Sense Amplifiers Flash Cell Array Block X Page Y Sense Amplifiers 6 Row Column

Flash Cell Floating Gate Gate Drain Source Floating Gate Transistor ( Flash Cell) V th = 2.5 V 7

Flash Read V read = 2.5 V V th = 3 V V th = 2 V 1 0 V read = 2.5 V 8 Gate

Flash Pass-Through V pass = 5 V V th = 2 V 1 V pass = 5 V 9 Gate 1 V th = 3 V

Read from Flash Cell Array 3.0V 3.8V 3.9V 4.8V 3.5V 2.9V 2.4V 2.1V 2.2V 4.3V 4.6V 1.8V 3.5V 2.3V 1.9V 4.3V V read = 2.5 V V pass = 5.0 V V pass = 5.0 V V pass = 5.0 V 1 1 0 0 Correct values for page 2: 10 Page 1 Page 2 Page 3 Page 4 Pass (5V) Read (2.5V) Pass (5V) Pass (5V)

Read Disturb Problem: “Weak Programming” Effect 3.0V 3.8V 3.9V 4.8V 3.5V 2.9V 2.4V 2.1V 2.2V 4.3V 4.6V 1.8V 3.5V 2.3V 1.9V 4.3V Repeatedly read page 3 (or any page other than page 2) 11 Read (2.5V) Pass (5V) Pass (5V) Pass (5V) Page 1 Page 2 Page 3 Page 4

V read = 2.5 V V pass = 5.0 V V pass = 5.0 V V pass = 5.0 V 0 1 0 0 Read Disturb Problem: “Weak Programming” Effect High pass-through voltage induces “weak-programming” effect 3.0V 3.8V 3.9V 4.8V 3.5V 2.9V 2.1V 2.2V 4.3V 4.6V 1.8V 3.5V 2.3V 1.9V 4.3V Incorrect values from page 2: 12 2.4V 2.6V Page 1 Page 2 Page 3 Page 4

Goal: Mitigate and Recover Read Disturb ErrorsRead disturb errors: Reading from one page can alter the values stored in other unread pages 13

OutlineBackground (Problem and Goal)Key Experimental ObservationsMitigation: V pass TuningRecovery: Read Disturb Oriented Error RecoveryConclusion14

MethodologyFPGA-based flash memory testing platform [Cai+, FCCM ‘11] Real 20- to 24-nm MLC NAND flash chips0 to 1M read disturbs0 to 15K Program/Erase Cycles (PEC)15

Read Disturb Effect on Vth Distribution Normalized Threshold Voltage × 10 -3 6 5 43 2 1 0 0 50 100 150 200 250 300 350 400 450 500 PDF 0 (No Read Disturbs) 0.25M Read Disturbs 0.5M Read Disturbs 1M Read Disturbs ER state P1 state P2 state P3 state V th gradually increases with read disturb counts 16

Other Experimental ObservationsLower threshold voltage states are affected more by read disturbWear-out increases read disturb effect 17

Reducing The Pass-Through Voltage18 Key Observation 1: Slightly lowering Vpass greatly reduces read disturb errors

OutlineBackground (Problem and Goal)Key Experimental ObservationsMitigation: Vpass Tuning Recovery: Read Disturb Oriented Error RecoveryConclusion19

Read Disturb Mitigation: Vpass TuningKey Idea: Dynamically find and apply a lowered VpassTrade-off for lowering VpassAllows more read disturbsInduces more read errors20

Read Errors Induced by Vpass Reduction21 3.0V 3.8V 3.9V 4.8V 3.5V 2.9V 2.4V 2.1V 2.2V 4.3V 4.6V 1.8V 3.5V 2.3V 1.9V 4.3V V read = 2.5 V V pass = 4.9 V V pass = 4.9 V V pass = 4.9 V 1 1 0 0 Reducing V pass to 4.9V Page 1 Page 2 Page 3 Page 4

Read Errors Induced by Vpass Reduction22 3.0V 3.8V 3.9V 4.8V 3.5V 2.9V 2.4V 2.1V 2.2V 4.3V 4.6V 1.8V 3.5V 2.3V 1.9V 4.3V V read = 2.5 V V pass = 4.7 V V pass = 4.7 V V pass = 4.7 V 1 0 0 0 Reducing V pass to 4.7V Incorrect values from page 2: Page 1 Page 2 Page 3 Page 4

Utilizing the Unused ECC Capability23 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 N -day Retention 1.0 0.8 0.6 0.4 0.2 0 RBER × 10 -3 ECC Correction Capability Unused ECC capability Huge unused ECC correction capability can be used to tolerate read errors 2. Unused ECC capability decreases over time Dynamically adjust V pass so that read errors fully utilize the unused ECC capability

Vpass Reduction Trade-Off SummaryConservatively set Vpass to a high voltage Accumulates more read disturb errors at the end of each refresh intervalNo read errorsDynamically adjust Vpass to unused ECC capabilityMinimize read disturb errorsControl read errors to be tolerable by ECCIf read errors exceed ECC capability, read again with a higher Vpass to correct read errors 24

Vpass Tuning StepsPerform once for each block every day:Estimate unused ECC capabilityAggressively reduce Vpass until read errors exceeds ECC capabilityGradually increase Vpass until read error just becomes less than ECC capability 25

Evaluation of Vpass Tuning19 real workload I/O tracesAssume 7-day refresh periodSimilar methodology as before to determine acceptable V pass reductionOverhead for a 512 GB flash drive:128 KB storage overhead for per-block Vpass setting and worst-case page24.34 sec/day average Vpass Tuning overhead26

Vpass Tuning Lifetime Improvements27 Vpass Tuning Average lifetime improvement: 21.0%

OutlineBackground (Problem and Goal)Key Experimental ObservationsMitigation: Vpass TuningRecovery: Read Disturb Oriented Error RecoveryConclusion28

Read Disturb Resistance29 RP Disturb-R esistant Disturb- P roneNormalized VthPDF N read disturbs N read disturbs R P

Observation 2: Some Flash Cells AreMore Prone to Read Disturb30 P1 ER Normalized V th PDF P P P P R P R P R P R P Disturb-prone cells have higher threshold voltages Disturb-resistant cells have lower threshold voltages After 250K read disturb: Disturb-prone ER state Disturb-resistant P1 state

Read Disturb Oriented Error Recovery (RDR)Triggered by an uncorrectable flash errorBack up all valid data in the faulty blockDisturb the faulty page 100K times (more)Compare Vth’s before and after read disturbSelect cells susceptible to flash errors (Vref−σ<Vth<Vref−σ) Predict among these susceptible cellsCells with more Vth shifts are disturb-prone  Higher V th state Cells with less Vth shifts are disturb-resistant  Lower Vth state31

RDR Evaluation32 × 10 -3 12 10 86 4 2 0 RBER Read Disturb Count 0 0.2M 0.4M 0.6M 0.8M 1 M No Recovery RDR Reduce total error counts up to 36% @ 1M read disturbs ECC can be used to correct the remaining errors

OutlineBackground (Problem and Goal)Key Experimental ObservationsMitigation: Vpass TuningRecovery: Read Disturb Oriented Error RecoveryConclusion33

Executive SummaryRead disturb errors limit flash memory lifetime today Apply a high pass-through voltage (Vpass) to multiple pages on a readWe characterize read disturb on real NAND flash chipsSlightly lowering Vpass greatly reduces read disturb errors Some flash cells are more prone to read disturbTechnique 1: Mitigate read disturb errors onlineVpass Tuning dynamically finds and applies a lowered VpassFlash memory lifetime improves by 21%Technique 2: Recover after failure to prevent data lossRead Disturb Oriented Error Recovery (RDR) selectively corrects cells more susceptible to read disturb errorsReduces raw bit error rate (RBER) by up to 36% 34

Read Disturb Errors in MLC NAND Flash Memory:Characterization, Mitigation, and Recovery Yu Cai, Yixin Luo, Saugata Ghose, Erich F. Haratsch*, Ken Mai, Onur MutluCarnegie Mellon University, *Seagate Technology