SCLS AUGUST  POST OFFICE BOX  DALLAS TEXAS  Can Be Used as Two Bit Counters or a Single Bit Counter V to
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SCLS AUGUST POST OFFICE BOX DALLAS TEXAS Can Be Used as Two Bit Counters or a Single Bit Counter V to

5V V CC Operation Max t pd of 25 ns at 5 V RCLK to Y Typical V OLP Output Ground Bounce 07 V at V CC 5 V T 25 Typical V OHV Output V OH Undershoot 44 V at V CC 5 V T 25 off Supports PartialPowerDown Mode Operation LatchUp Performance Exceeds 250

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SCLS AUGUST POST OFFICE BOX DALLAS TEXAS Can Be Used as Two Bit Counters or a Single Bit Counter V to




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SCLS589 AUGUST 2004 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Can Be Used as Two 16-Bit Counters or a Single 32-Bit Counter 2-V to 5.5-V V CC Operation Max t pd of 25 ns at 5 V (RCLK to Y) Typical V OLP (Output Ground Bounce) <0.7 V at V CC = 5 V, T = 25 Typical V OHV (Output V OH Undershoot) >4.4 V at V CC = 5 V, T = 25 off Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101)

description/ordering information The SN74LV8154 is a dual 16-bit binary counter with 3-state output registers, designed for 2-V to 5.5-V V CC operation. This 16-bit counter (A or B) feeds a 16-bit storage register, and each storage register is further divided into an upper byte and lower byte. The GAL , GAU , GBL , GBU inputs are used to select the byte that needs to be output at Y0−Y7. CLKA is the clock for A counter, and CLKB is the clock for B counter. RCLK is the clock for the A and B storage registers. All three clock signals are positive-edge triggered. A 32-bit counter can be

realized by connecting CLKA and CLKB together and by connecting RCOA to CLKBEN To ensure the high-impedance state during power up or power down, GAL , GAU , GBL , and GBU should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using I off . The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP

− N Tube SN74LV8154N SN74LV8154N −40 C to 85 TSSOP − PW Tube SN74LV8154PW LV8154 −40 C to 85 TSSOP − PW Tape and reel SN74LV8154PWR LV8154 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. N OR PW PACKAGE (TOP VIEW) CLKA CLKB GAL GAU GBL GBU RCLK RCOA CLKBEN GND CC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 CCLR 10 20 19 18 17 16 15 14 13 12 11 Copyright 2004, Texas Instruments Incorporated Please be aware that an important notice concerning avail ability, standard warranty, and use in

critical applications o Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. !"#$ % &'!!($ #% )'*+&#$ ,#$(- !,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2 #++ )#!#"($(!%-


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SCLS589 AUGUST 2004 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 FUNCTION TABLE (each buffer) INPUTS OUTPUT GAL GAU GBL GBU OUTPUT Yn Lower byte in A register L H H Upper byte in A register H L H Lower byte in B register H H L Upper byte in B register Combinations of GAL , GAU , GBL , GBU , other than those shown above, are prohibited. If more than one input is L at the same time, the output data (Y0−Y7) may be invalid. timing diagram 0000 0001 0002 0003 0004 0100 0101 0102 0103 FFFD FFFE FFFF 0000 0001 0000 0001 0002 0003 0004 0100 0101 0102 FFFD FFFE FFFF 0000 0001 Don’t

Care 00 01 02 03 00 FF 01 CCKBEN CCLR CCKA CCKB RCLK Counter Counter GAL GAU GBL GBU Output RCOA
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SCLS589 AUGUST 2004 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 block diagram CCKB CCKBEN RCLK CCKA CCLR RRRRRRRRRRRRRRRR RRRR RRRRRRRRRRR 16-Bit Counter B 16-Bit Counter A GAL GAU GBL GBU 4 to 1 Dec 4 to 1 Dec 4 to 1 Dec 4 to 1 Dec 4 to 1 Dec 4 to 1 Dec 4 to 1 Dec 4 to 1 Dec Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 RCOA absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC −0.5 V to 7 V . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range, V (see Note 1) −0.5 V to 7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage range applied to any output in the high-impedance or power-off state, V (see Note 1) −0.5 V to 7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output voltage range, V (see Notes 1 and 2) −0.5 V to V CC + 0.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input clamp current,

I IK (V < 0) −20 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output clamp current, I OK (V < 0) −50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous output current, I (V = 0 to V CC ) 35 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous current through V CC or GND 70 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, JA (see Note 3): N package 69 C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PW package 83 C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, T stg −65 C to 150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated

under “recommended operating conditi ons” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
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SCLS589 AUGUST 2004 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 recommended operating conditions (see Note 4) CC MIN MAX UNIT CC Supply voltage 5.5 2 V 1.5 IH High-level input voltage 3 V to

3.6 V CC 0.7 IH High-level input voltage 4.5 V to 5.5 V CC 0.7 2 V 0.5 IL Low-level input voltage 3 V to 3.6 V CC 0.3 IL Low-level input voltage 4.5 V to 5.5 V CC 0.3 Input voltage 5.5 Output voltage High or low state CC Output voltage 3-state 5.5 2 V −50 Yn outputs 3 V to 3.6 V −6 mA OH High-level output current Yn outputs 4.5 V to 5.5 V −12 mA OH High-level output current 2 V −50 RCOA 3 V to 3.6 V −6 mA RCOA 4.5 V to 5.5 V −12 mA 2 V 50 Yn outputs 3 V to 3.6 V mA OL Low-level output current Yn outputs 4.5 V to 5.5 V 12 mA OL Low-level output current 2 V 50

RCOA 3 V to 3.6 V mA RCOA 4.5 V to 5.5 V 12 mA t/ Input transition rise or fall rate 3 V to 3.6 V 100 ns/V t/ Input transition rise or fall rate 4.5 V to 5.5 V 20 ns/V Operating free-air temperature −40 85 NOTE 4: All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs , literature number SCBA004.
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SCLS589 AUGUST 2004 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) PARAMETER TEST CONDITIONS CC MIN TYP MAX UNIT OH = −50 2 V 1.9 Yn OH = −6 mA 3 V 2.48 OH Yn OH = −12 mA 4.5 V 3.8 OH OH = −50 2 V 1.9 RCOA OH = −6 mA 3 V 2.48 RCOA OH = −12 mA 4.5 V 3.8 OL = 50 2 V 0.1 Yn OL = 6 mA 3 V 0.44 OL Yn OL = 12 mA 4.5 V 0.55 OL OL = 50 2 V 0.1 RCOA OL = 6 mA 3 V 0.44 RCOA OL = 12 mA 4.5 V 0.55 = 5.5 V or GND 0 to 5.5 V OZ = V CC or GND 5.5 V CC = V CC or GND, I = 0 5.5 V 20 off or V = 0 to 5.5 V = V CC or GND 5 V pF = V CC or GND 5 V pF timing requirements over recommended operating free-air temperature range, V CC

= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1) MIN MAX UNIT Pulse duration CLKA, CLKB, RCLK high or low 10 ns Pulse duration CCLR low 22 ns CLKBEN low before CLKB 13 CCLR high (inactive) before CLKA or CLKB 13 su Setup time CLKA or CLKB before RCLK 13 ns su Setup time RCLK before GAL or GAU or GBL or GBU low 13 ns GAL or GAU or GBL or GBU high (inactive) before RCLK 13 Hold time CLKBEN low after CLKB ns Hold time CLKA or CLKB after RCLK ns Z-period GAL , GAU , GBL , GBU all high before one of them switches low 200 ns condition: C = 50 pF, R = 1 k
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SCLS589 AUGUST 2004

POST OFFICE BOX 655303 DALLAS, TEXAS 75265 timing requirements over recommended operating free-air temperature range, V CC = 5 V 0.5 V (unless otherwise noted) (see Figure 1) MIN MAX UNIT Pulse duration CLKA, CLKB, RCLK high or low 10 ns Pulse duration CCLR low 20 ns CLKBEN low before CLKB 10 CCLR high (inactive) before CLKA or CLKB 10 su Setup time CLKA or CLKB before RCLK 10 ns su Setup time RCLK before GAL or GAU or GBL or GBU low 10 ns GAL or GAU or GBL or GBU high (inactive) before RCLK 10 Hold time CLKBEN low after CLKB ns Hold time CLKA or CLKB after RCLK ns Z-period GAL , GAU , GBL ,

GBU all high before one of them switches low 200 ns condition: C = 50 pF, R = 1 k switching characteristics over recommended operating free-air temperature range, CC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM TO LOAD = 25 MIN MAX UNIT PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE MIN TYP MAX MIN MAX UNIT MAX = 15 pF 40 MHz MAX = 50 pF 25 MHz pd RCLK 22 38 ns pd CLKA RCOA 26 44 ns PLH CCLR RCOA = 15 pF 18 32 ns en GAL , GAU , GBL , GBU = 15 pF 27 46 ns dis GAL , GAU , GBL , GBU 12 21 ns pd RCLK 25 42 ns pd CLKA RCOA 28 46 ns PLH CCLR RCOA = 50 pF 20 35 ns en GAL

, GAU , GBL , GBU = 50 pF 30 50 ns dis GAL , GAU , GBL , GBU 14 24 ns
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SCLS589 AUGUST 2004 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range, CC = 5 V 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM TO LOAD = 25 MIN MAX UNIT PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE MIN TYP MAX MIN MAX UNIT MAX = 15 pF 40 MHz MAX = 50 pF 25 MHz pd RCLK 14 25 ns pd CLKA RCOA 16 27 ns PLH CCLR RCOA = 15 pF 12 20 ns en GAL , GAU , GBL , GBU = 15 pF 16 28 ns dis GAL , GAU , GBL , GBU 15 ns pd RCLK 16 27

ns pd CLKA RCOA 17 28 ns PLH CCLR RCOA = 50 pF 13 21 ns en GAL , GAU , GBL , GBU = 50 pF 18 30 ns dis GAL , GAU , GBL , GBU 16 ns noise characteristics, V CC = 5 V, C = 50 pF PARAMETER = 25 UNIT PARAMETER MIN TYP MAX UNIT OL(P) Quiet output, maximum dynamic V OL 0.7 OL(V) Quiet output, minimum dynamic V OL −0.75 OH(V) Quiet output, minimum dynamic V OH 4.4 operating characteristics, V CC = 5 V, T = 25 PARAMETER TEST CONDITIONS TYP UNIT pd Power dissipation capacitance = No load, CCLK = 10 MHz, RCLK = 1 MHz 56 pF
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SCLS589 AUGUST 2004 POST OFFICE BOX 655303 DALLAS, TEXAS

75265 PARAMETER MEASUREMENT INFORMATION 50% V CC CC CC 0 V 0 V su VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Data Input PLH PHL PHL PLH OH OH OL OL CC 0 V 50% V CC 50% V CC Input Out-of-Phase Output In-Phase Output Timing Input 50% V CC VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Control Output Waveform 1 S1 at V CC (see Note B) Output Waveform 2 S1 at GND (see Note B) OL OH PZL PZH PLZ PHZ CC 0 V 50% V CC OL + 0.3 V 50% V CC 0 V CC VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING PLH /t PHL PLZ /t PZL PHZ /t PZH Open Drain Open CC GND

CC TEST S1 CC 0 V 50% V CC VOLTAGE WAVEFORMS PULSE DURATION Input NOTES: A. C includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, Z = 50 , t 3 ns, t 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. t PLZ and t PHZ are

the same as t dis F. t PZL and t PZH are the same as t en G. t PHL and t PLH are the same as t pd H. All parameters and waveforms are not applicable to all devices. From Output Under Test (see Note A) LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS S1 CC = 1 k GND From Output Under Test (see Note A) Test Point LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS Open 50% V CC 50% V CC 50% V CC 50% V CC 50% V CC 50% V CC 50% V CC 50% V CC OH 0.3 V Figure 1. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page PACKAGING INFORMATION Orderable Device

Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74LV8154N ACTIVE PDIP 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74LV8154N SN74LV8154NE4 ACTIVE PDIP 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74LV8154N SN74LV8154PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV8154 SN74LV8154PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV8154 SN74LV8154PWR ACTIVE TSSOP PW 20 2000 Green

(RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LV8154 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan

- The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI

Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The

Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2014 Addendum-Page (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are

underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual

basis. OTHER QUALIFIED VERSIONS OF SN74LV8154 : Enhanced Product: SN74LV8154-EP NOTE: Qualified Version Definitions: Enhanced Product - Supports Defense, Aerospace and Medical Applications
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