PPT-Branch Hazards Consider executing this sequence of instructions in the pipeline:

address instruction 36 sub 10 4 8 40 beq 1 3 72 44 and 12 2 5 48 or 13 1213 52 add 14 4 2. Prof. Hakim Weatherspoon. CS 3410, . Spring 2015. Computer Science. Cornell University. See P&H Chapter: . 4.6-4.8. Announcements. Prelim next week. . Tuesday at 7:30. . Go to location based . on . Computer Organization . and Architecture. 7. th. Edition. Chapter 12. CPU Structure and Function. Group 5. . Chris Bello. Arnold . Colina. . Edemio. . Navas. . Rieni. Gonzalez . CPU Structure. 5. Branch Prediction . (2.3) and . Scoreboarding. (A.7). 2. Why do we want to predict branches?. MIPS based pipeline – 1 instruction issued per cycle, branch hazard of 1 cycle.. Delayed branch. Modern processor and next generation – multiple instructions issued per cycle, more branch hazard cycles will incur.. Consider executing this sequence of instructions in the pipeline:. address instruction. ----------------------------. 36: sub $10, $4, $8. 40: . beq. $1, $3, 72. 44: and $12, $2, $5. Situations that prevent starting the next instruction in the next . cycle. Structural hazards. A required resource is busy. Data hazard. Need to wait for previous instruction to complete its data read/write. Two forms of pipelining. Instruction unit. overlap fetch-execute cycle so that multiple instructions are being processed at the same time, each instruction in a different portion of the fetch-execute cycle. and Instruction Variations. Hakim Weatherspoon. CS 3410, . Spring 2012. Computer Science. Cornell University. See P&H . Appendix. . 4.8. Goals for Today. Recap: Data Hazards. Control Hazards. What is the next instruction to execute if a branch is taken? Not taken?. Two forms of pipelining. Instruction unit. overlap fetch-execute cycle so that multiple instructions are being processed at the same time, each instruction in a different portion of the fetch-execute cycle. Performance. The speed at which a computer executes a program is affected by . the design of its hardware – processor speed, clock rate, memory access time etc.. the machine language (ML) instructions – the instruction format, instruction set etc. Now that we’ve seen the basic design elements for modern processors, we will take a look at several specific processors. We start with the 486 pipeline to see how NOT to do a pipeline. recall . Intel x86 is a CISC with variable length instructions, memory-register addressing, some complex addressing modes and some complex instructions . Situations that prevent starting the next instruction in the next . cycle. Structural hazards. A required resource is busy. Data hazard. Need to wait for previous instruction to complete its data read/write. cycle. Structural hazards. A required resource is busy. Data hazard. Need to wait for previous instruction to complete its data read/write. Control hazard. Deciding on control action depends on previous instruction. Professor Alvin R. Lebeck. Computer Science 220 / ECE 252. Fall 2008. Admin. Homework #1 Due Today. Homework #2 Assigned. Reading. H&P Chapter 2 & 3 (suggested). Research papers (not yet ready to read, but will be soon!):. Lecture 32: Pipeline Parallelism 3. Instructor: . Dan Garcia. inst.eecs.Berkeley.edu. /~cs61c. You Are Here!. Parallel Requests. Assigned to computer. e.g., Search “Katz”. Parallel Threads. Assigned to core.