Mokhov Victor Khomenko Arseniy Alekseyev Alex Yakovlev Algebra of Parameterised Graphs Motivation Design cost is the greatest threat to the semiconductors roadmap manufacturing takes weeks with low ID: 525224
Download Presentation The PPT/PDF document "Andrey" is the property of its rightful owner. Permission is granted to download and print the materials on this web site for personal, non-commercial use only, and to display it on your personal computer provided you do not modify the materials and that you retain all copyright notices contained in the materials. By downloading content from our website, you accept the terms of this agreement.
Slide1
Andrey Mokhov, Victor KhomenkoArseniy Alekseyev, Alex Yakovlev
Algebra of Parameterised GraphsSlide2
MotivationDesign cost is the greatest threat
to the semiconductors roadmap:manufacturing takes weeks, with low uncertaintydesign takes months or years, with high
uncertaintyDesigner has to
explore a large design space, and thus comprehend a huge number ofsystem configurationsoperational modesbehavioural scenariosimplementation choices
Infeasible to consider each individual mode, need toexploit similarities between the individual modes
work with groups of modes rather than individual onesmanage the modes and groups of modes compositionallytransform/optimise specs in a formal and natural waySlide3
Design productivity gap10000py
Annual productivity gain ~20%
Annual manufacturing gain >40%
850py
“Productivity gap”Slide4
?
13 lines
270 stations
Individual descriptionsSlide5
Easier for comprehension and reasoning
Gives bigger picture of the system
Easier to modify than individual lines
Orange
Park
Overlaid descriptions
?Slide6
Characteristics of components
2-input adder
3-input adder
2-input multiplier
fast 2-input multiplier
dedicated DP3 unit
Design space exploration
DP3(
x
,
y
)=x
1
y
1
+ x
2
y2 + x3y3Slide7
Fastest
Design space exploration
2 multipliers
Least peak power
Dedicated
component
BalancedSlide8
Operations on graphs:
overlay G
1
+G
2
+==+Slide9
Operations on graphs:
sequence G
1
G
2
==Slide10
Operations on graphs: condition [x]G[0]G= (empty graph)[1]G=G
From arithmetic to algebra: use parameters
[x]GSlide11
Operations on graphs: condition [x]G[0]G= (empty graph)[1]G=G
From arithmetic to algebra: use parameters
[x]GSlide12
Operations on graphs: condition [x]G[0]G= (empty graph)[1]G=G
From arithmetic to algebra: use parameters
[x]G
[1]
[0]
?[x]Slide13
Canonical form of PGs Proposition: Any PG can be rewritten in the following canonical form
: whereV is a subset of singleton graphs that appear in the original PG
b
v are canonical forms of Boolean expressionsbuv are canonical forms of Boolean expressions, s.t. buv
⇒ bubvSlide14
Algebra of PGsWe define the equivalence relation on PGs abstractly, using the following axioms:
+ is commutative and associative is associative is a left and right identity of
left- and right-distributes over +
Decomposition: p q r = p q + p
r + q rCondition: [0]p = and [1]p = p
Theorem: The set of axioms of PG-algebra is soundminimalcomplete w.r.t. PGsSlide15
Useful equalities (proved from axioms)
is an identity of ++ is idempotent Left/right absorption:p + p
q = p qq
+ p q = p q Conditional : [x]
= Conditional + and :[x](p + q) = [x]p + [x]q[x](p q) = [x]p
[x]q AND-condition: [x y]p = [x][y]p OR-condition: [x y]p = [x]p + [y]pSlide16
Case study: phase encoderPhase encoding: data is encoded by the order of arrival of signals on n wires:
Goal: synthesise matrix phase encoderInputs: dual-rail ports xij that specify the order of signals
Outputs: phase encoded data v
i
abdc
n! scenariosSlide17
Case study: phase encoderOverall specification: where Hij
models behaviour of ith and jth output wiresIf x
ij=1 and x
ji=0 then there is a causal dependency vi vjIf
xij=0 and xji=1 then there is a causal dependency vj
viIf xij=xji=0 then neither vi nor vj can be produced yet; this is expressed by a circular wait condition between vi and vj|H| and the resulting circuit are linear in the size of input!Slide18
Transitive Parameterised Graphs is often interpreted as causal dependency, so the graphs are
transitiveHence two graphs are considered equal iff their transitive closures are equalCan express this by an additional axiom Closure:
if q then p
q + q r = p q + p
r + q rOften allows to simplify expressions by transitive reductionSlide19
Transitive parameterised graphs
PG expression
[x](
(a + b)
c + cd) + [x]((a + b)(d + e))with the specialisationsTPG expression (a + b)([x]cd + [x]e)with the specialisationsSlide20
Canonical form of TPGs Proposition: Any TPG can be rewritten in the following canonical form
: whereV is a subset of singleton graphs that appear in the original TPG
bv
are canonical forms of Boolean expressionsbuv are canonical forms of Boolean expressions, s.t. buv
⇒ bubvtransitivity: for all
u,v,w∈V, buv bvw ⇒ buw Slide21
TPG axioms – minimal, sound, completeTheorem: The set of axioms of TPG-algebra is sound
minimalcomplete w.r.t. TPGs.Slide22
Case study: Processor microcontroller
?Slide23
Case study: Processor microcontrollerInstructions classes:ALU Rn to Rn
e.g. ADD A,B; MOV A,BALU #123 to Rn e.g. SUB A,#1; MOV B,#3ALU Rn to PC e.g. JMP A
ALU #123 to PC e.g. JMP #2012
Memory access e.g. MOV A,[B]; MOV [B],ACond. ALU Rn to
Rn e.g. if A<B then ADD A,BCond. ALU #123 to Rn e.g. if A<B then SUB A,#1
Cond. ALU #123 to PC e.g. if A<B then JMP #2012Slide24
Case study: Processor microcontrollerALU #123 to Rn e.g. SUB A,#1; MOV B,#3
TPG algebra specification:PCIU IFU (ALU + PCIU’)
IFU’
The graph is considered up to transitivitySlide25
Case study: Processor microcontrollerCond. ALU #123 to Rn e.g. if A<B then SUB A,#1
If A < B holds:(ALU + PCIU)
IFU
(ALU’ + PCIU’
) IFU’If A < B does not hold:
(ALU + PCIU) PCIU’ IFU’Composing the two scenarios, lt := (A<B):[lt]((ALU + PCIU) IFU (ALU’ + PCIU’) IFU’)+[lt]((ALU + PCIU) PCIU’ IFU’)=(ALU + PCIU) [lt]IFU (PCIU’ + [lt]ALU’) IFU’Slide26
Case study: Processor microcontrollerCond. ALU #123 to Rn e.g. if A<B then SUB A,#
1(ALU + PCIU) [lt]IFU
(PCIU’ + [lt]ALU’)
IFU’Slide27
Case study: Processor microcontrollerSlide28
Case study: Processor microcontrollerSlide29
Conclusions and future workNew formalisms: PG and TPG algebrae with sound, minimal and complete sets of axiomsCanonical formsCan work with groups
of scenarios and exploit the similarities between themCan formally compose, manipulate and simplify the specifications using the rules of these algebraeApplications in microelectronics, formal methods, computer architecture, modelling university courses
Future work:Tool implementation
Simplification by modular decomposition of graphsSlide30
Thank you!