EOC architecture Bus system Low swing signaling crosscoupled lines noise SNR TOT discriminator TDC readout 6 October 2008 1 GTK design review pjarron NA62 GTK ASIC Motivation to develop EOC architecture ID: 1000634
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1. Overview of the EOC architectureEOC architecture, Bus system, Low swing signaling, cross-coupled lines, noise SNR, TOT discriminator, TDC, readout6 October 20081GTK design review p.jarron NA62 GTK ASIC
2. Motivation to develop EOC architectureMinimize digital noise in the pixel areaWhy?Severe risk of coupling between analog/digital in GHz domainExist already in working pixel detectorsAsynchronous hit events with readout clock makes noise rejection tougher than LHC pixelSimultaneous read/writeNo hit data reductionAll hits are readout making no difference between on-pixel and off-pixel processingPrecautions taken in the EOC ASICNo digital circuits in the active beam area, No clock “ “ “Push all digital circuits in the end of column TDC circuits onlyBus system using differential current drive and very low voltage swing 15 mV at the far end TDC end of column circuitUse a TOT discriminator having a smaller analog bandwidth than a CFD stageBut a larger digital bandwidth if no time walk calculation is done on-chipProfit from the existing TDC development in 130 nmTDC in the end of column bank is a 100 ps version of Christian ‘s design6 October 20082GTK design review p.jarron NA62 GTK ASIC
3. Overall EOC-TDC architecture EOC architecture No digital processing in pixel TDC, Time stamping and data pipelining in end of column DLL based digital TDC Time walk correction by a time over threshold discriminator Column pixel addresses encoded with a 5 x 9 matrix Bus system using cross coupled transmission lines, low current swing signal , with pre-emphasis for dispersive loss compensation3459Ref CLK40 MHzzDLL 32-bitTDC bankaddressRX5TDC bankaddressRX5TDC bankaddressRX5TDC bankaddressRX5999PLL 320 MHz40registersserial.registersserial.registersserial.registersserial.Multiport gigabit link~ 5 Gbit/s40 columns of 14 lines/45 pixels6 October 2008GTK design review p.jarron NA62 GTK ASIC
4. EOC column circuitColumn block diagram6 October 20084GTK design review p.jarron NA62 GTK ASIC
5. Encoding pixel addressBus system architecturePixel address is encoded by a 5x9 networked busDecreases the number of TDC from 45 to 9, factor 5 smaller1800 double-TDC bank to 360 double TDCThe only issue is the pile up on data lineNo problem of pile up for address line6 October 20085GTK design review p.jarron NA62 GTK ASIC
6. NINO circuit TOT discri6 October 20086GTK design review p.jarron NA62 GTK ASIC
7. Cross-coupled waveguide14.0. Shielded Transmission Line Interconnect Models. The current design kit release includes models for the following topologies:" Straight single wire shielded transmission line, thereafter referred to as SINGLEWIRE." Two straight wires shielded transmission line, thereafter referred to as COUPLEDWIRE." Straight single wire coplanar waveguide, thereafter referred to as SINGLECPW." Two straight wires coplanar waveguide, thereafter referred to as COUPLEDCPW.Note: All interconnect models included in the current release are symmetrical and supported for both MA and LM CMRF8SF BEOL metal options.6 October 2008GTK design review p.jarron NA62 GTK ASIC7
8. Transmission line IBM models and layoutgrounded lines has been chosen to avoid crosstalk between bus line 6 October 2008GTK design review p.jarron NA62 GTK ASIC8
9. From pixel to end of column 9 Data lines have 5 pixels attached, each driver delivering 50 µA on the line: total 2x 250 µA5 Address lines have 9 pixels attached, each driver delivering 20 µA, a Total of 2x180 µAOptimization not yet done with pre-emphasis, DC bias current might be lowerTransmission line (wave guide) has a odd impedance of about 40 ΩTermination impedance is much higher, in the order of 200/300 ΩNo reflection observed on simulation, explained by dispersive lossy linespixelEOC6 October 20089GTK design review p.jarron NA62 GTK ASIC
10. 130 nm IBM CMOS8RF DM noise analysis, silicon sensor signalPreamp noise ENC f(Cd)Parallel and series noiseDrain current 40 µA, leakage current 20 nA5 ns peaking time – shaping equivalent to CR-RC2Input transistor optimizationSeries noise only6 October 2008GTK design review p.jarron NA62 GTK ASIC10Risk of ballistic deficitSilicon sensor signal formationAt saturation velocity
11. Modeling of the pixel sensorSilicon sensorThickness 150 /200 µmCpp= 60 fFCpg= 80 fFIdet , 3 ns pulse, from 0.8 to 3.2 fC, > 95% of eventsDiamond sensor?ButLot of uncertainty of capacitancePrecise modeling would be welcome6 October 200811NA62 GigaTracker meeting pierre jarron
12. Pixel cellAnalogue, no digital circuit6 October 2008GTK design review p.jarron NA62 GTK ASIC123 fC inputScan input chargeFrom 0.6 fC to 3.2 fCCrosstalk <5%
13. Noise simulation at minimum signal of 0.75fCTransient noise simulation CPP=60 fF, CPG=80 fFQdet=0.75 fC, VT=42 mVClose-up, Width= 5ns,Jitter without TOT correction: 150 ps r.m.s6 October 200813NA62 GigaTracker design review pierre jarron
14. End of column processingEnd of column blockTime Measurement Unit and pix addressDLL based TDC, 32 delay cells, 100 ps bin6 October 2008p.jarron NA62 GTK ASIC design review14Hit.reg17-bitencoderTime Measurement Unit Common to a column of 45 pixels7320 MHzCoarsecounter77SenseampDiscr.5Address encoder& MUX9 linesDLLt0,t1,t3,…,tN-2,tN-1Hit.reg2τ0τ1τN-2τN-1PDCP VCDLUPDOWNRef CLKDLL CLKVCTRLt0t1tN-2tN-1
15. Power budget/pixel cellcomponentCurrent (µA)Voltage (V)Power (µW)preamp401.248amp401.248discriminator401,248Driver data100 (50)0.440 (20)Driver Add40 (20)0.416 (8)Total 260 (190)202 (175)6 October 2008GTK design review p.jarron NA62 GTK ASIC15Power budget/EOC columncomponentCurrent (µA)Voltage (V)Power (µW)receiver100 (50)0.8 80 (40) x 14= 1.12DLL 1.2 TDC 1,2 Total
16. LM DM options6 October 2008GTK design review p.jarron NA62 GTK ASIC16
17. DM option selected 6 October 2008GTK design review p.jarron NA62 GTK ASIC17
18. Summary of the EOC overviewPixel cellPreamplifier works fine with ENC<200 rms e-Discriminator width is linear with amplitudeWalk easily corrected down to less than 100 ps Concept of transmission line based bus systemLooks working well with pre-emphasisEncoding 9x5 bus has an efficiency dependent of the max pulse widthReceiver circuit inspired from NINO looks goodPower optimization not yet doneOffset compensation to be doneEnd of column TDCLooks O.K though very denseProblem of top simulationSimulation with Spectre with complex (top) analog circuitProblems after problems with the DM design kit, much less with LM?Submission in NovemberLooks difficult, I prefer to postpone in January6 October 2008GTK design review p.jarron NA62 GTK ASIC18