T arget State of the art silicon detectors 10 cm d μ e μ 50 cm Detector Optimization 2 T arget State of the art silicon detectors d μ e μ L 3 Intrinsic resolution ID: 780303
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Slide1
Detector optimizationTrigger
Slide2T
arget
State of the art silicon detectors
10
cm
d
μ
e
μ
50 cm
Detector Optimization
2
Slide3T
arget
State of the art silicon detectors
d
μ
e
μ
L
3
Intrinsic resolution ~
sqrt
(2) dx /
L
eff
Slide4Detector resolution
Slide5Slide6CMS CBC ASIC
Slide7Foreseen max trigger latency 12.8
μs
Maximum trigger rate 750 kHz
Slide8Slide9STUB
Use stubs for triggering
MUOnE
T
arget
State of the art silicon detectors
d
μ
e
μ
L
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Reference clock
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Reference clock
Trigger
Trigger
Trigger
μ
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μ
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Slide12Reference clock
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Trgger